DS1643 ,Nonvolatile Timekeeping RAMFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock, VN.C. 1 28 CCCrystal, Power-Fail ..
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DS1643-100+ ,Nonvolatile Timekeeping RAMFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock, VN.C. 1 28 CCCrystal, Power-Fail ..
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DTV110 ,CRT HORIZONTAL DEFLECTION HIGH VOLTAGE DAMPER DIODEFEATURES AND BENEFITSHIGH BREAKDOWN VOLTAGE CAPABILITYISOWATT220ACTO-220ACVERY FAST RECOVERY DIODED ..
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DS1643
Nonvolatile Timekeeping RAM
FEATURES Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit and
Lithium Energy Source Clock Registers are Accessed Identically to the
Static RAM. These Registers Reside in the
Eight Top RAM Locations. Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power Access Times of 85ns and 100ns BCD-Coded Year, Month, Date, Day, Hours,
Minutes, and Seconds with Leap Year
Compensation Valid Up to 2100 Power-Fail Write Protection Allows for ±10%
VCC Power Supply Tolerance Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until Power
is Applied for the First Time DS1643 Only (DIP Module)
Standard JEDEC Byte-Wide 8K x 8 RAM
Pinout UL Recognized DS1643P Only (PowerCap Module Board)
Surface Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Power-Fail Output
Pin-for-Pin Compatible with Other Densities of
DS164XP Timekeeping RAM
PIN CONFIGURATIONS
ORDERING INFORMATION
PART VOLTAGE RANGE
(V) TEMP RANGE PIN-PACKAGE TOP MARK
DS1643-85+ 5.0 0°C to +70°C 28 EDIP (0.740) DS1643+85
DS1643-100+ 5.0 0°C to +70°C 28 EDIP (0.740) DS1643+100
DS1643P-85+ 5.0 0°C to +70°C 34-PowerCap* DS1643P+85
DS1643P-100+ 5.0 0°C to +70°C 34-PowerCap* DS1643P+100
*DS9034I-PCX+ and DS9034-PCX+ required (must be ordered separately).
+Denotes a lead(Pb)-free/RoHS-compliant package. The top mark will include a “+” symbol on lead-free devices.
DS1643/DS1643P
Nonvolatile Timekeeping RAMs
27
Encapsulated DIP
(700-mil Extended) DQ0
DQ1
GND
DQ2
VCC
CE2
A11
A10
DQ7
DQ6
DQ5
DQ3
DQ4
28
26
25
24
23
22
21
20
19
18
17
15
16
A12
N.C.
DS1643 N.C.2 N.C.
N.C.
PFOVCC CEDQ7DQ6
DQ5DQ4
DQ3
DQ2DQ1
DQ0
GND5 6 9
10
11 12
13 14
15
16 17
N.C.N.C.33 32
31 30
29
28 27 26
25
24 23
22
21 20
19 18
N.C.
A12A11
A10A9A8A6A4A2
34 N.C.
X1 GND VBAT X2
PowerCap Module Board
(Uses DS9034PCX PowerCap)
DS1643P TOP VIEW
19-5058; Rev 5/10
DS1643/DS1643P
PIN DESCRIPTION
PIN
PDIP PowerCap NAME FUNCTION 1, 2, 3,
31–34 N.C. No Connection
2 30 A12
3 25 A7
4 24 A6
5 23 A5
6 22 A4
7 21 A3
8 20 A2
9 19 A1
10 18 A0
21 28 A10
23 29 A11
24 27 A9
25 26 A8
Address Inputs
11 16 DQ0
12 15 DQ1
13 14 DQ2
15 13 DQ3
16 12 DQ4
17 11 DQ5
18 10 DQ6
19 9 DQ7
Data Input/Output
20 8 CE Active-Low Chip-Enable Input
22 7 OE Active-Low Output-Enable Input
26 — CE2 Chip-Enable 2 Input (Active High)
27 6 WE Active-Low Write-Enable Input
28 5 VCC Power-Supply Input
— 4 PFO Active-Low Power-Fail Output. This open-drain pin requires a
pullup resistor for proper operation.
14 17 GND Ground
— X1, X2,
VBAT Crystal Connection, Battery Connection
DS1643/DS1643P
DESCRIPTION The DS1643 is an 8K x 8 nonvolatile static RAM with a full function Real Time Clock (RTC) that are
both accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to
any JEDEC standard 8K x 8 SRAM. The device can also be easily substituted in ROM, EPROM and
EEPROM sockets providing read/write nonvolatility and the addition of the real time clock function. The
real time clock information resides in the eight uppermost RAM locations. The RTC registers contain
year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day
of the month and leap year are made automatically. The RTC clock registers are double-buffered to
avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also
prevents time loss as the timekeeping countdown continues unabated by access to time register data. The
DS1643 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in
an out of tolerance condition. This feature prevents loss of data from unpredictable system operation
brought on by low VCC as errant access and update cycles are avoided.
PACKAGES The DS1643 is available in two packages: 28-pin DIP module and 34-pin PowerCap module. The 28-pin
DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1643P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1643 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a one is written into the read bit, the seventh most significant bit in the control
register. As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers
reflect the count, that is day, date, and time that was current at the moment the halt command was issued.
However, the internal clock registers of the double-buffered system continue to update so that the clock
accuracy is not affected by the access of data. All of the DS1643 registers are updated simultaneously
after the clock status is reset. Updating is within a second after the read bit is written to 0.
DS1643/DS1643P
Figure 1. Block Diagram
Table 1. Truth Table
VCC CE CE2 OE WE MODE DQ POWER VIH X X X Deselect High Z Standby
X VIL X X Deselect High Z Standby
VIL VIH X VIL Write Data In Active
VIL VIH VIL VIH Read Data Out Active
5V 10%
VIL VIH VIH VIH Read High-Z Active
<4.5V >
VBAT X X X X Deselect High-Z CMOS Standby
SETTING THE CLOCK
The 8-bit of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts updates
to the DS1643 registers. The user can then load them with the correct day, date and time data in 24 hour
BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and
allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting it to
a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for access remain valid
(i.e., CE low, OE low, CE2 high, and address for seconds register remain valid and stable).
DS1643/
DS1643P
DS1643/DS1643P
CLOCK ACCURACY (DIP MODULE)
The DS1643 is guaranteed to keep time accuracy to within 1 minute per month at 25C.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1643P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within 1.53 minutes per month (35ppm) at 25C.
Table 2. Register Map—Bank1
DATA ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 FUNCTION RANGE
1FFF — — — — — — — — Year 00-99
1FFE X X X — — — — — Month 01-12
1FFD X X — — — — — — Date 01-31
1FFC X Ft X X X — — — Day 01-07
1FFB X X — — — — — — Hour 00-23
1FFA X — — — — — — — Minutes 00-59
1FF9 OSC — — — — — — — Seconds 00-59
1FF8 W R X X X X X X Control A
OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST
W = WRITE BIT X = UNUSED
Note: All indicated “X” bits are not used but must be set to “0” for proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1643 is in the read mode whenever WE (write enable) is high and CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before tAA , the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1643 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
DS1643/DS1643P
DATA RETENTION MODE
When VCC is within nominal limits (VCC > 4.5V) the DS1643 can be accessed as described above with
read or write cycles. However, when VCC is below the power-fail point VPF (point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-on reset output signal (RST) will
be driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the
level of the internal battery supply, power input is switched from the VCC pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal
level. The RST signal is an open drain output and requires a pull up. Except for the RST, all control, data,
and address signals must be powered down when VCC is powered down.
BATTERY LONGEVITY
The DS1643 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1643 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25C with the internal clock oscillator running in
the absence of VCC power. Each DS1643 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
Ds1643 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.
DS1643/DS1643P
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………..-0.3V to +6.0V
Operating Temperature Range………………………………………………0°C to +70°C, Noncondensing
Storage Temperature (EDIP) ……………………………………………-40°C to +85°C, Noncondensing
Storage Temperature (PowerCap) ………………………………………-55°C to +125°C, Noncondensing
Lead Temperature (soldering, 10 seconds)………………………… . . . . . . . . . . . . . . . . . . . . ……+260°C
Note: EDIP is hand or wave-soldered only (Note 7).
Soldering Temperature (PowerCap reflow) . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0C to +70C)
PARAMETER SYMBOLMIN TYP MAX UNITS NOTES
Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 Voltage All Inputs VIH 2.2 VCC + 0.3 V
Logic 0 Voltage All Inputs VIL -0.3 +0.8 V
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 10%, TA = 0C to70C.)
PARAMETER SYMBOLMIN TYP MAX UNITS NOTES
Active Supply Current ICC 15 50 mA 2, 3
TTL Standby Current CE = VIH, CE2 = VIL) ICC1 1 3 mA 2, 3
CMOS Standby Current CE = VCC - 0.2V, CE2 = GND + 0.2V) ICC2 1 3 mA 2, 3
Input Leakage Current (Any Input) IIL -1 +1 A
Output Leakage Current (Any Output) IOL -1 +1 A
Output Logic 1 Voltage
(IOUT = -1.0mA) VOH 2.4 1
Output Logic 0 Voltage
(IOUT = +2.1mA) VOL 0.4 1
Write Protection Voltage VPF 4.25 4.37 4.50 V 1
DS1643/DS1643P
AC CHARACTERISTICS—READ CYCLE
(VCC = 5.0V 10%, TA = 0C to +70C.)
85ns
ACCESS
100ns
ACCESS PARAMETER SYMBOL
MIN MAX MIN MAX
UNITS NOTES
Read Cycle Time tRC 85 100 ns 4
Address Access Time tAA 85 100 ns 4 and CE2 to DQ Low-Z tCEL 5 5 ns 4 Access Time tCEA 85 100 ns 4
CE2 Access Time tCE2A 95 105 ns 4 and CE2 Data Off Time tCEZ 30 35 ns 4 to DQ Low-Z tOEL 5 5 ns 4 Access Time tOEA 45 55 ns 4 Data Off Time tOEZ 30 35 ns 4
Output Hold from Address tOH 5 5 ns 4
READ CYCLE TIMING DIAGRAM
DS1643/DS1643P
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5.0V 10%, TA = 0C to +70C.)
85ns
ACCESS
100ns
ACCESS PARAMETER SYMBOL
MIN MAX MIN MAX
UNITS NOTES
Write Cycle Time tWC 85 100 ns 4
Address Setup Time tAS 0 0 ns 4 Pulse Width tWEW 65 70 ns 4 Pulse Width tCEW 70 75 ns 4
CE2 Pulse Width tCE2W 75 85 ns 4
Data Setup Time tDS 35 40 ns 4
Data Hold Time tDH 0 0 ns 4
Address Hold Time tAH 5 5 ns 4 Data Off Time tWEZ 30 35 ns 4
Write Recovery Time tWR 5 5 ns 4
