DS1642 ,Nonvolatile Real Time Clocks RAMPIN DESCRIPTION PIN NAME FUNCTION 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 Address Input 7 A1 8 A0 19 A10 22 A ..
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DS1642-100+ ,Nonvolatile Timekeeping RAMPIN DESCRIPTION PIN NAME FUNCTION 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 Address Input 7 A1 8 A0 19 A10 22 A ..
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DS1643-100 ,Nonvolatile Timekeeping RAMBLOCK DIAGRAM Figure 1CLOCKOSCILLATOR ANDREGISTERS32.768 KHzCLOCK COUNTDOWNCHAINCEWE8K X 8 NV SRAMO ..
DS1643-100 ,Nonvolatile Timekeeping RAMFEATURES PIN ASSIGNMENT• Form, fit, and function compatible with the MK48T08NC 1 28 VCCTimekeeping ..
DTTI5516AUA ,DTTI5516 SINGLE MODULE DEMODULATOR AND DECODER IC FOR DIGITAL VIDEO SET-TOP BOXES Data Briefing®DTTi5516Single module demodulator and decoder ICfor digital video set-top boxesDATA BRIEFDescripti ..
DTV110 ,CRT HORIZONTAL DEFLECTION HIGH VOLTAGE DAMPER DIODEFEATURES AND BENEFITSHIGH BREAKDOWN VOLTAGE CAPABILITYISOWATT220ACTO-220ACVERY FAST RECOVERY DIODED ..
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DTV1500 ,CRT HORIZONTAL DEFLECTION HIGH VOLTAGE DAMPER DIODEABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Repetitive peak reverse voltage 1500 VRRMI RMS ..
DTV1500H ,HIGH VOLTAGE DAMPER DIODE (CRT HORIZONTAL DEFLECTION)ABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Repetitive peak reverse voltage 1500 VRRMI RMS ..
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DS1642
Nonvolatile Real Time Clocks RAM
FEATURES Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit, and
Lithium Energy Source Standard JEDEC Bytewide 2k x 8 Static
RAM Pinout Clock Registers are Accessed Identically to
the Static RAM. These Registers are
Resident in the Eight Top RAM Locations Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power Access Times of 85ns and 100ns Quartz Accuracy ±1 Minute a Month at
+25°C, Factory Calibrated BCD-Coded Year, Month, Date, Day, Hours,
Minutes, and Seconds with Leap Year
Compensation Valid Up to 2100 Power-Fail Write Protection Allows for
±10% VCC Power Supply Tolerance Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time UL Recognized
PIN CONFIGURATION
ORDERING INFORMATION
PART
VOLTAGE
RANGE
(V)
TEMP RANGE PIN-PACKAGETOP MARK DS1642-85+ 5.0 0°C to +70°C 24 EDIP (0.720a) DS1642+85
DS1642-100+ 5.0 0°C to +70°C 24 EDIP (0.720a) DS1642+100
+Denotes a lead(Pb)-free/RoHS-compliant package.
A “+" indicates a lead(Pb)-free product. The top mark will include a “+” symbol on lead-free devices.
DS1642
Nonvolatile Timekeeping RAM
VCC
A8
A9
A10
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
DQ7
DQ6
DQ5
DQ4
DQ3
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DS1642
ENCAPSULATED DIP TOP VIEW
19-5266; Rev 5/10
DS1642
PIN DESCRIPTION
PIN NAME FUNCTION 1 A7
2 A6
3 A5
4 A4
5 A3
6 A2
7 A1
8 A0
19 A10
22 A9
23 A8
Address Input
9 DQ0
10 DQ1
11 DQ2
13 DQ3
14 DQ4
15 DQ5
16 DQ6
17 DQ7
Data Input/Output
12 GND Ground
18 CE Active-Low Chip-Enable Input
20 OE Active-Low Output-Enable Input
21 WE Active-Low Write-Enable Input
24 VCC Power-Supply Input
DESCRIPTION The DS1642 is a 2k x 8 nonvolatile static RAM and a full-function real-time clock (RTC), both of which
are accessible in a bytewide format. The nonvolatile time keeping RAM is pin and function equivalent to
any JEDEC-standard 2k x 8 SRAM. The device can also be easily substituted in ROM, EPROM, and
EEPROM sockets, providing read/write nonvolatility and the addition of the real-time clock function. The
real-time clock information resides in the eight uppermost RAM locations. The RTC registers contain
year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day
of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid
access of incorrect data that can occur during clock update cycles. The double-buffered system also
prevents time loss as the timekeeping countdown continues unabated by access to time register data. The
DS1642 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in
an out-of-tolerance condition. This feature prevents loss of data from unpredictable system operation
brought on by low VCC as errant access and update cycles are avoided.
DS1642
CLOCK OPERATIONS–READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1642 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was current at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1642 registers are updated simultaneously after the clock
status is reset. Updating occurs within a second after the read bit is written to 0.
Figure 1. DS1642 BLOCK DIAGRAM
Table 1. TRUTH TABLE
VCC CE OE WE MODE DQ POWER VIH X X Deselect High-Z Standby
VIL X VIL Write Data In Active
VIL VIL VIH Read Data Out Active 5V ±10%
VIL VIH VIH Read High-Z Active
<4.5V > VBAT X X X Deselect High-Z CMOS Standby
DS1642
SETTING THE CLOCK
The 8th bit of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts
updates to the DS1642 registers. The user can then load them with the correct day, date and time data in
24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters
and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting it to
a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid
(i.e., CE low, and OE low) and address for seconds register remain valid and stable.
CLOCK ACCURACY
The DS1642 is guaranteed to keep time accuracy to within 1 minute per month at 25C. Dallas
Semiconductor calibrates the clock at the factory by using special calibration nonvolatile-tuning elements.
The DS1642 does not require additional calibration and temperature deviations will have a negligible
effect in most applications. For this reason, methods of field clock calibration are not available and not
necessary.
Table 2. REGISTER MAP–BANK1
DATA ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 FUNCTION
7FF — — — — — — — — Year 00–99
7FE X X X — — — — — Month 01–12
7FD X X — — — — — — Date 01–31
7FC X FT X X X — — — Day 00–23
7FB X X — — — — — — Hour 00–59
7FA X — — — — — — — Minutes 00–59
7F9 OSC — — — — — — — Seconds 00–59
7F8 W R X X X X X X Control A
OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST
W = WRITE BIT X = UNUSED
Note: All indicated “X” bits are not used but must be set to “0” during write cycle to ensure proper clock
operation.
DS1642
RETRIEVING DATA FROM RAM OR CLOCK
The DS1642 is in the read mode whenever WE (write enable) is high, and CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before tAA, the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1642 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
When VCC is within nominal limits (VCC > 4.5V) the DS1642 can be accessed as described above by read
or write cycles. However, when VCC is below the power-fail point VPF (point at which write protection
occurs) the internal clock registers and RAM is blocked from access. This is accomplished internally by
inhibiting access via the CE signal. When VCC falls below the level of the internal battery supply, power
input is switched from the VCC pin to the internal battery and clock activity, RAM, and clock data are
maintained from the battery until VCC is returned to nominal level.
BATTERY LONGEVITY
The DS1642 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1642 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25C with the internal clock oscillator running in
the absence of VCC power. Each DS1642 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1642 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.
DS1642
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………..-0.3V to +6.0V
Operating Temperature Range……………………………………………...0°C to +70°C (noncondensing)
Storage Temperature Range…………………………………………… -40°C to +85°C (noncondensing)
Lead Temperature (soldering, 10 seconds)
Note: Hand or wave-soldered only (Note 6) …………. . . . . . . . . . ………..………. . . . . . . …..+260C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Logic 1 Voltage
(All Inputs) VIH 2.2 VCC + 0.3V 1
Logic 0 Voltage
(All Inputs) VIL -0.3 0.8 V 1
DC ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Active Supply Current ICC 15 50 mA 2, 3
TTL Standby Current CE = VIH) ICC1 1 3 mA 2, 3
CMOS Standby Current CE < VCC - 0.2V) ICC2 1 3 mA 2, 3
Input Leakage Current
(Any Input) IIL -1 +1 A
I/O Leakage Current
(Any Output) IOL -1 +1 A
Output Logic 1 Voltage
(IOUT = -1.0mA) VOH 2.4 1
Output Logic 0 Voltage
(IOUT = +2.1mA) VOL 0.4 1
Write Protection Voltage VPF 4.25 4.37 4.50 V 1
DS1642
AC CHARACTERISTICS—READ CYCLE
85ns ACCESS 100ns ACCESS PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Read Cycle Time tRC 85 100 ns
Address Access Time tAA 85 100 ns to DQ Low-Z tCEL 5 5 ns Access Time tCEA 85 100 ns Data Off Time tCEZ 30 35 ns to DQ Low-Z tOEL 5 5 ns Access Time tOEA 45 55 ns Data Off Time tOEZ 30 35 ns
Output Hold from Address tOH 5 5 ns
READ CYCLE TIMING DIAGRAM
