DS1609 Fast Delivery |IC PHOENIX CO.,LIMITED

DS1609 ,Dual port RAM, 256朾ytePIN DESCRIPTIONAD0–AD7 – Port address/dataCE – Port enableWE – Write enableOE – Output enableV – +5 ..
DS1609-50 ,Dual Port RAMPIN DESCRIPTIONAD0–AD7 – Port address/dataCE – Port enableWE – Write enableOE – Output enableV – +5 ..
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DS1609
Dual port RAM, 256朾yte
DS1609
Dual Port RAM
DS1609
020499 1/7
FEATURESTotally asynchronous 256–byte dual port memoryMultiplexed address and data bus keeps pin count
lowDual port memory cell allows random access with
minimum arbitrationEach port has standard independent RAM control sig-
nalsFast access timeLow power CMOS design24–pin DIP or 24–pin SOIC surface mount packageBoth CMOS and TTL compatibleOperating temperature of –40°C to +85°CStandby current of 100 nA @ 25°C makes the device
ideal for battery backup or battery operate applica-
tions.
PIN ASSIGNMENT
DS1609S
24–PIN SOIC (300 MIL)
VCC
OEB
CEB
WEB
AD0B
AD1B
AD2B
AD3B
AD4B
AD5B
AD6B
AD7B
AD7A
AD6A
AD5A
AD4A
AD3A
AD2A
AD1A
AD0A
WEA
CEA
OEA
GND
PORT A
DS1609
24–PIN DIP (600 MIL)
PORT A
VCC
OEB
CEB
WEB
AD0B
AD1B
AD2B
AD3B
AD4B
AD5B
AD6B
AD7B
AD7A
AD6A
AD5A
AD4A
AD3A
AD2A
AD1A
AD0A
OEA
GND
See Mech. Drawings
Section
See Mech. Drawings
Section
PORT B
PIN DESCRIPTION
AD0–AD7–Port address/data–Port enable–Write enable–Output enable
VCC–+5 volt supply
GND–Ground
DESCRIPTION
The DS1609 is a random access 256–byte dual port
memory designed to connect two asyncronous ad-
dress/data buses together with a common memory ele-
ment. Both ports have unrestricted access to all
256 bytes of memory, and with modest system disci-
pline no arbitration is required. Each port is controlled
by three control signals: output enable, write enable,
and port enable. The device is packaged in plastic
24–pin DIP and 24–pin SOIC. Output enable access
time of 50 ns is available when operating at 5 volts.
DS1609
020499 2/7
OPERATION – READ CYCLE
The main elements of the dual port RAM are shown in
Figure 1.
A read cycle to either port begins by placing an address
on the multiplexed bus pins AD0 – AD7. The port enable
control (CE) is then transitioned low. This control signal
causes address to be latched internally. Addresses can
be removed from the bus provided address hold time is
met. Next, the output enable control (OE) is transitioned
low, which begins the data access portion of the read
cycle. With both CE and OE active low, data will appear
valid after the output enable access time tOEA. Data will
remain valid as long as both port enable and output en-
able remains low. A read cycle is terminated with the
first occurring rising edge of either CE or OE. The ad-
dress/data bus will return to a high impedance state af-
ter time tCEZ or tOEZ as referenced to the first occurring
rising edge. WE must remain high during read cycles.
OPERATION – WRITE CYCLE
A write cycle to either port begins by placing an address
on the multiplexed bus pins AD0 – AD7. The port enable
control (CE) is then transitioned low. This control signal
causes address to be latched internally. As with a read
cycle, the address can be removed from the bus pro-
vided address hold time is met. Next the write enable
control signal (WE) is transitioned low which begins the
write data portion of the write cycle. With both CE and
WE active low the data to be written to the selected
memory location is placed on the multiplexed bus. Pro-
vided that data setup (tDS) and data hold (tDH) times are
met, data is written into the memory and the write cycle
is terminated on the first occurring rising edge of either
CE or WE. Data can be removed from the bus as soon
as the write cycle is terminated. OE must remain high
during write cycles.
ARBITRATION
The DS1609 dual port RAM has a special cell design
that allows for simultaneous accesses from two ports
(see Figure 2). Because of this cell design, no arbitra-
tion is required for read cycles occurring at the same in-
stant. However, an argument for arbitration can be
made for reading and writing the cell at the exact same
instant or for writing from both ports at the same instant.
A simple way to assure that read/write conflicts don’t oc-
cur is to perform redundant read cycles. Write/write ar-
bitration needs can be avoided by assigning groups of
addresses for write operation to one port only. Groups
of data can be assigned check sum bytes which would
system using a “mail box” to pass status information can
also be employed. Each port could be assigned a
unique byte for writing status information which the oth-
er port would read. The status information could tell the
reading port if any activity is in progress and indicate
when activity is going to occur.
DS1609
020499 3/7
BLOCK DIAGRAM: DUAL PORT RAM Figure 1
PORT A
MUX ADDRESS/DATA
PORT B
DUAL PORT MEMORY CELL Figure 2
DATA–PORT A
DATA–PORT B
DS1609
020499 4/7
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground–0.5V to +7.0V
Operating Temperature–40°C to +85°C
Storage Temperature–55°C to +125°C
Soldering Temperature260°C for 10 secondsThis is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (–40°C to +85°C)
CAPACITANCE (tA = 25°C)
DS1609
020499 5/7
AC ELECTRICAL CHARACTERISTICS (–40°C to +85°C; VCC = 5V ± 10%)
DS1609
020499 6/7
DUAL PORT RAM TIMING: READ CYCLE
DURING READ CYCLE WE = VIH
tAS
NOTES:During read cycle the address must be off the bus prior to tOEA minimum to avoid bus contention.Read cycles are terminated by the first occurring rising edge of OE or CE.
DUAL PORT RAM TIMING: WRITE CYCLE
DURING WRITE CYCLE OE = VIH
tAS
tWP
NOTE:Write cycles are terminated by the first occurring edge of WE or CE.

Partno	Mfg	Dc	Qty	Available	Descript
DS1609	DALLAS	N/a	2000	avai	Dual port RAM, 256朾yte