DS1556WP-120 ,1M, Nonvolatile, Y2K-Compliant Timekeeping RAMPIN DESCRIPTION A0–A16 - Address Input DQ0–DQ7 - Data Input/Outputs IRQ/FT - Interrupt, Freque ..
DS1556WP-120 ,1M, Nonvolatile, Y2K-Compliant Timekeeping RAMPIN DESCRIPTION A0–A16 - Address Input DQ0–DQ7 - Data Input/Outputs IRQ/FT - Interrupt, Freque ..
DS1556WP-120 ,1M, Nonvolatile, Y2K-Compliant Timekeeping RAMFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock (RTC), Crystal, Power-Fail Cont ..
DS1556WP-120 ,1M, Nonvolatile, Y2K-Compliant Timekeeping RAM DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
DS1556WP-120+ ,1M, Nonvolatile, Y2K-Compliant Timekeeping RAM19-5500; Rev 9/10 DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
DS1557P-70 ,4MEG NV Y2KC Timekeeping RAMPRELIMINARYDS15574MEG NV Y2KC Timekeeping RAMwww.dalsemi.com
DTC314TS , Digital transistors (built-in resistor)
DTC314TU , Digital transistors (built-in resistor)
DTC323TS , Digital transistors (built-in resistor)
DTC323-TS , Digital transistors (built-in resistor)
DTC343TS , Digital transistors (built-in resistor)
DTC363EU , Digital transistors (built-in resistors)
DS1556-70-DS1556P-70-DS1556W-120-DS1556WP+120-DS1556WP-120
1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
FEATURES ��Integrated NV SRAM, Real-Time Clock
(RTC), Crystal, Power-Fail Control Circuit,
and Lithium Energy Source
��Clock Registers are Accessed Identically to
the Static RAM; These Registers Reside in
the 16 Top RAM Locations
��Century Byte Register (i.e., Y2K Compliant)
��Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power
��Precision Power-On Reset
��Programmable Watchdog Timer and RTC
Alarm
��BCD-Coded Year, Month, Date, Day, Hours, Minutes, and seconds with Automatic Leap-
Year Compensation Valid Up to the Year
2100
��Battery Voltage-Level Indicator Flag
��Power-Fail Write Protection Allows for �10%
VCC Power-Supply Tolerance
��Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
��Also Available in Industrial Temperature
Range: -40°C to +85°C
PIN CONFIGURATIONS
DS15561M, Nonvolatile, Y2K-Compliant
Timekeeping RAMPowerCap is a registered trademark of Dallas Semiconductor.
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
PIN DESCRIPTION A0–A16 - Address Input
DQ0–DQ7 - Data Input/Outputs
IRQ/FT - Interrupt, Frequency Test Output (Open Drain)
RST - Power-On Reset Output (Open Drain)
CE - Chip Enable
OE - Output Enable
WE - Write Enable
VCC - Power Supply Input
GND - Ground
N.C. - No Connection
X1, X2 - Crystal Connection
VBAT - Battery Connection
ORDERING INFORMATION
DESCRIPTION The DS1556 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) with an
RTC alarm, watchdog timer, power-on reset, battery monitor, and 128k x 8 nonvolatile static RAM. User
access to all registers within the DS1556 is accomplished with a byte-wide interface as shown in Figure 1. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour
BCD format. Corrections for day of month and leap year are made automatically.
The RTC registers are double-buffered into an internal and external set. The user has direct access to the
external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers is
continuously updated, which occurs regardless of external registers settings to guarantee that accurate
RTC information is always maintained.
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
match user programmed alarm values. The interrupt is always available while the device is powered from
the system supply and can be programmed to occur when in the battery-backed state to serve as a system wake-up. Either the IRQ/FT or RST outputs can also be used as a CPU watchdog timer, CPU activity is
monitored and an interrupt or reset output will be activated if the correct activity is not detected within
programmed limits. The DS1556 power-on reset can be used to detect a system power down or failure
and hold the CPU in a safe reset state until normal power returns and stabilizes; the RST output is used
for this function.
The DS1556 also contains its own power-fail circuitry, which automatically deselects the device when the
VCC supply enters an out of tolerance condition. This feature provides a high degree of data security
during unpredictable system operation brought on by low VCC levels.
PACKAGES The DS1556 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1556P after the completion of the surface mount process. Mounting the PowerCap after the surface mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
Figure 1. Block Diagram DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
Table 1. Operating Modes
DATA-READ MODE The DS1556 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that CE and OE access times are
satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable
access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is
controlled by CE and OE. If the outputs are activated before tAA, the data lines are driven to an
intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address
access.
DATA-WRITE MODE The DS1556 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout the
cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In
a typical application, the OE signal will be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
DATA-RETENTION MODE The 5V device is fully accessible and data can be written and read only when VCC is greater than VPF.
However, when VCC is below the power-fail point VPF (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium
battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The 3.3V device is fully accessible and data can be written and read only when VCC is greater than VPF.
hen VCC falls below VPF, access to the device is inhibited. If VPF is less than VSO, the device power is
switched from VCC to the internal backup lithium battery when VCC drops below VPF. If VPF is greater than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops
below VSO. RTC operation and SRAM data are maintained from the battery until VCC is returned to
nominal levels.
All control, data, and address signals must be powered down when VCC is powered down.
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
BATTERY LONGEVITY The DS1556 has a lithium power source that is designed to provide energy for the clock activity, and
clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1556 continuously for the life of the equipment in which it is
installed. For specification purposes, the life expectancy is 10 years at 25�C with the internal clock
oscillator running in the absence of VCC. Each DS1556 is shipped from Dallas Semiconductor with its
lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a
level greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1556 will be much longer than 10 years since no internal battery energy is
consumed when VCC is present.
INTERNAL BATTERY MONITOR The DS1556 constantly monitors the battery voltage of the internal battery. The Battery Low Flag (BLF)
bit of the Flags Register (B4 of 1FFF0h) is not writable and should always be a 0 when read. If a 1 is ever present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are
questionable.
POWER-ON RESET A temperature compensated comparator circuit monitors the level of VCC. When VCC falls to the power
fail trip point, the RST signal (open drain) is pulled low. When VCC returns to nominal levels, the RST
signal continues to be pulled low for a period of 40 ms to 200 ms. The power-on reset function is independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.
CLOCK OPERATIONS Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions.
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
Table 2. Register Map X = Unused, Read/Writable Under Write and Read Bit Control AE = Alarm Flag Enable
Y = Unused, Read/Writable Without Write and Read Bit Control ABE = Alarm in Battery-Backup Mode Enable
FT = Frequency Test Bit AM1 to AM4 = Alarm Mask Bits
OSC = Oscillator Start/Stop Bit WF = Watchdog Flag
W = Write Bit AF = Alarm Flag
R = Read Bit 0 = 0 (Read Only)
WDS = Watchdog Steering Bit BLF = Battery Low Flag
BMB0 to BMB4 = Watchdog Multiplier Bits RB0 to RB1 = Watchdog Resolution Bits
CLOCK OSCILLATOR CONTROL The clock oscillator can be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the
MSB of the Seconds Register (B7 of 1FFF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the
oscillator. The DS1556 is shipped from Dallas Semiconductor with the clock oscillator turned off, OSC
bit set to a 1.
READING THE CLOCK When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
Registers. This puts the external registers into a static state allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register (1FFF8h). As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is
issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt
command was issued. Normal updates to the external set of registers will resume within 1 second after the
read bit is set to a 0 for a minimum of 500 �s. The read bit must be a zero for a minimum of 500 �s to
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
SETTING THE CLOCK The MSB bit, B7, of the Control Register is the write bit. Setting the write bit to a 1, like the read bit,
halts updates to the DS1556 (1FFF8h to 1FFFFh) registers. After setting the write bit to a 1, RTC Registers can be loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting
the write bit to a 0 then transfers the values written to the internal RTC Registers and allows normal
operation to resume.
CLOCK ACCURACY (DIP MODULE) The DS1556 is guaranteed to keep time accuracy to within �1 minute per month at 25�C. The RTC is calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. The electrical environment also affects clock accuracy, and caution should be taken to place
the RTC in the lowest-level EMI section of the PC board layout. For additional information, please refer
to Application Note 58.
CLOCK ACCURACY (PowerCap MODULE) The DS1556 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within �1.53 minutes per month (35 ppm) at 25°C. The
electrical environment also affects clock accuracy, and caution should be taken to place the RTC in the
lowest-level EMI section of the PC board layout. For additional information, please refer to Application Note 58.
FREQUENCY TEST MODE The DS1556 frequency test mode uses the open drain IRQ/FT output. With the oscillator running, the
IRQ/FT output will toggle at 512 Hz when the FT bit is a 1, the Alarm Flag Enable bit (AE) is a 0, and
the Watchdog Steering bit (WDS) is a 1 or the Watchdog Register is reset (Register 1FFF7h = 00h). The
IRQ/FT output and the frequency test mode can be used as a measure of the actual frequency of the
32.768 kHz RTC oscillator. The IRQ/FT pin is an open-drain output that requires a pullup resistor for proper operation. The FT bit is cleared to a 0 on power-up.
USING THE CLOCK ALARM The alarm settings and control for the DS1556 reside within Registers 1FFF2h to 1FFF5h. Register
1FFF6h contains two alarm enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE
and ABE bits must be set as described below for the IRQ/FT output to be activated for a matched alarm condition.
The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,
minute, or second. It can also be programmed to go off while the DS1556 is in the battery-backed state of operation to serve as a system wake-up. Alarm mask bits AM1 to AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in the table default to the once per second mode to
notify the user of an incorrect alarm setting.
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
Table 3. Alarm Mask Bits When the RTC Register values match Alarm Register settings, the Alarm Flag bit (AF) is set to a 1. If
Alarm Flag Enable (AE) is also set to a 1, the alarm condition activates the IRQ/FT pin. The IRQ/FT signal is cleared by a read or write to the Flags Register (Address 1FFF0h) as shown in Figure 2 and 3.
When CE is active, the IRQ/FT signal may be cleared by having the address stable for as short as 15 ns
and either OE or WE active, but is not guaranteed to be cleared unless tRC is fulfilled. The alarm flag is
also cleared by a read or write to the Flags Register but the flag will not change states until the end of the
read/write cycle and the IRQ/FT signal has been cleared.
Figure 2. Clearing IRQ Waveforms
Figure 3. Clearing IRQ Waveforms The IRQ/FT pin can also be activated in the battery-backed mode. The IRQ/FT will go low if an alarm
occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm
timing during the battery-backup mode and power-up states.
Figure 4. Backup Mode Alarm Waveforms
USING THE WATCHDOG TIMER The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog
timer by setting the desired amount of time-out into the 8-bit Watchdog Register (Address 1FFF7h). The
five Watchdog Register bits BMB4 to BMB0 store a binary multiplier and the two lower order bits RB1 to RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The
watchdog timeout value is then determined by the multiplication of the 5-bit multiplier value with the
2-bit resolution value. (For example: writing 00001110 in the Watchdog Register = 3 x 1 second or
3 seconds.) If the processor does not reset the timer within the specified period, the Watchdog Flag (WF)
is set and a processor interrupt is generated and stays active until either the Watchdog Flag (WF) is read or the Watchdog Register (1FFF7h) is read or written.
The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a 0,
the watchdog will activate the IRQ/FT output when the watchdog times out. When WDS is set to a 1, the watchdog will output a negative pulse on the RST output for a duration of
40 ms to 200 ms. The Watchdog Register (1FFF7h) and the FT bit will reset to a 0 at the end of a
watchdog timeout when the WDS bit is set to a 1.
The watchdog timer resets when the processor performs a read or write of the Watchdog Register. The time-out period then starts over. The watchdog timer is disabled by writing a value of 00h to the
Watchdog Register. The watchdog function is automatically disabled upon power-up and the Watchdog
Register is cleared. If the watchdog function is set to output to the IRQ/FT output and the frequency test
function is activated, the watchdog function prevails and the frequency test function is denied.
POWER-ON DEFAULT STATES Upon application of power to the device, the following register bits are set to a 0: WDS = 0, BMB0 to BMB4 = 0, RB0 to RB1 = 0, AE = 0, ABE = 0.
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………..………………………………………-0.3V to +6.0V
Storage Temperature Range………………………………………………………………………………...-40°C to +85°C Soldering Temperature………………………………………………….See IPC/JEDEC Standard J-STD-020A (Note 8)
for Surface-Mount Devices
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
RECOMMENDED DC OPERATING CONDITIONS (Over the Operating Range)
DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V �10%, Over the Operating Range.)
