DS1553-100+ ,64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAMFEATURES The DS1553 is a full-function, year-2000- Integrated NV SRAM, RTC, Crystal, Power-Fail Co ..
DS1553-70 ,64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAMPIN DESCRIPTION A0A12 - Address Input DQ0DQ7 - Data Input/Outputs IRQ /FT - Interrupt, Frequen ..
DS1553P-100 ,4MEG NV Y2KC Timekeeping RAMFEATURES The DS1553 is a full-function, year-2000-compliant Integrated NV SRAM, RTC, Crystal, Po ..
DS1553P-100+ ,64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM19-5480; Rev 8/10 DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
DS1553P-70 ,4MEG NV Y2KC Timekeeping RAMPIN DESCRIPTION A0A12 - Address Input DQ0DQ7 - Data Input/Outputs IRQ /FT - Interrupt, Frequen ..
DS1553P-70 ,4MEG NV Y2KC Timekeeping RAM DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
DTC144WS , DTA/DTC SERIES
DTC314TS , Digital transistors (built-in resistor)
DTC314TU , Digital transistors (built-in resistor)
DTC323TS , Digital transistors (built-in resistor)
DTC323-TS , Digital transistors (built-in resistor)
DTC343TS , Digital transistors (built-in resistor)
DS1553-100+-DS1553P-100+-DS1553W-120+
64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
GENERAL DESCRIPTION The DS1553 is a full-function, year-2000-
compliant (Y2KC) real-time clock/calendar (RTC)
with an RTC alarm, watchdog timer, power-on
reset, battery monitor, and 8k x 8 nonvolatile static
RAM. User access to all registers within the
DS1553 is accomplished with a byte-wide
interface as shown in Figure 1. The RTC registers
contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour BCD format.
Corrections for day of month and leap year are
made automatically.
Pin Configurations appear at end of data sheet.
FEATURES Integrated NV SRAM, RTC, Crystal, Power-Fail
Control Circuit, and Lithium Energy Source Clock Registers are Accessed Identically to the
Static RAM; These Registers are Resident in the
16 Top RAM Locations Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power Precision Power-On Reset Programmable Watchdog Timer and RTC Alarm BCD-Coded Year, Month, Date, Day, Hours,
Minutes, and Seconds with Automatic Leap Year
Compensation Valid Up to the Year 2100 Battery Voltage Level Indicator Flag Power-Fail Write Protection Allows for 10%
VCC Power-Supply Tolerance Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until Power is
Applied for the First Time
ORDERING INFORMATION
PART VOLTAGE (V) TEMP RANGE PIN-PACKAGE TOP MARK** DS1553-85+ 5.0 0°C to +70°C 28 EDIP (0.740) DS1553+85
DS1553-100+ 5.0 0°C to +70°C 28 EDIP (0.740) DS1553+100
DS1553W-120+ 3.3 0°C to +70°C 28 EDIP (0.740) DS1553W+120
DS1553W-150+ 3.3 0°C to +70°C 28 EDIP (0.740) DS1553W+150
DS1553P-85+ 5.0 0°C to +70°C 34 PowerCap* DS1553P+85
DS1553P-100+ 5.0 0°C to +70°C 34 PowerCap* DS1553P+100
DS1553WP-120+ 3.3 0°C to +70°C 34 PowerCap* DS1553WP+120
DS1553WP-150+ 3.3 0°C to +70°C 34 PowerCap* DS1553WP+150
DS9034PCX+ 3 0°C to +70°C — DS9034PCX
+Denotes a lead(Pb)-free/RoHS-compliant package.
*PowerCap required, must be ordered separately
**A “+” symbol anywhere on the top mark indicates a lead(Pb)-free package.
DS1553
64kB, Nonvolatile, Year-2000-Compliant
Timekeeping RAM
19-5480; Rev 8/10
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
PIN DESCRIPTION
PIN
EDIP PowerCap NAME FUNCTION 1 2 RST Active-Low Power-On Reset Output (Open Drain)
2 30 A12
3 25 A7
4 24 A6
5 23 A5
6 22 A4
7 21 A3
8 20 A2
9 19 A1
10 18 A0
21 28 A10
23 29 A11
24 27 A9
25 26 A8
Address Inputs
11 16 DQ0
12 15 DQ1
13 14 DQ2
15 13 DQ3
16 12 DQ4
17 11 DQ5
18 10 DQ6
19 9 DQ7
Data Input/Outputs
20 8 CE Active-Low Chip Enable
22 7 OE Active-Low Output Enable
26 1 IRQ/FT Active-Low Interrupt/Frequency Test Output (Open Drain)
27 6 WE Active-Low Write Enable
28 5 VCC Power-Supply Input
17 GND Ground 2, 3, 31–34 N.C No Connection
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
DETAILED DESCRIPTION The RTC registers in the DS1553 are double-buffered into an internal and external set. The user has direct
access to the external set. Clock/calendar updates to the external set of registers can be disabled and
enabled to allow the user to access static data. Assuming the internal oscillator is turned on, the internal
set of registers is continuously updated. This occurs regardless of external registers settings to guarantee
that accurate RTC information is always maintained.
The DS1553 has interrupt (IRQ/FT) and reset (RST) outputs that can be used to control CPU activity.
The IRQ/FT interrupt output can be used to generate an external interrupt when the RTC register values
match user-programmed alarm values. The interrupt is always available while the device is powered from
the system supply, and it can be programmed to occur when in the battery-backed state to serve as a
system wakeup. Either the IRQ/FT or RST outputs can also be used as a CPU watchdog timer. CPU
activity is monitored and an interrupt or reset output is activated if the correct activity is not detected
within programmed limits. The DS1553 power-on reset can be used to detect a system power-down or
failure and can hold the CPU in a safe reset state until normal power returns and stabilizes. The RST
output is used for this function.
The DS1553 also contains its own power-fail circuitry, which automatically deselects the device when the
VCC supply enters an out-of-tolerance condition. This feature provides a high degree of data security
during unpredictable system operation brought on by low VCC levels.
PACKAGES The DS1553 is available in a 28-pin DIP and a 34-pin PowerCap module. The 28-pin DIP module
integrates the crystal, lithium energy source, and silicon in one package. The 34-pin PowerCap module
board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the
crystal and battery. This design allows the PowerCap to be mounted on top of the DS1553P after
completion of the surface-mount process. Mounting the PowerCap after the surface-mount process
prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The
PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap are ordered
separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX.
Figure 1. Block Diagram DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
Table 1. Operating Modes
VCC CE OE WE
DQ0–DQ7 MODE POWER VIH X X High-Z Deselect Standby
VIL X VIL DIN Write Active
VIL VIL VIH DOUT Read Active
VCC > VPF
VIL VIH VIH High-Z Read Active
VSO < VCC
DATA READ MODE
The DS1553 is in read mode whenever CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data is available at
the data input/output (DQ) pins within tAA after the last address input is stable, provided that CE and OE
access times are satisfied. If CE or OE access times are not met, valid data is available at the latter of
chip-enable access (tCEA) or at output-enable access time (tOEA). The state of the DQ pins is controlled by and OE. If the outputs are activated before tAA, the data lines are driven to an intermediate state until
tAA. If the address inputs are changed while CE and OE remain valid, output data remains valid for
output data hold time (tOH) but will then go indeterminate until the next address access.
DATA WRITE MODE
The DS1553 is in write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout
the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent
read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH
afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
The 5V device is fully accessible, and data can be written and read only when VCC is greater than VPF.
However, when VCC is below the power-fail point (VPF)—the point at which write protection occurs—the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium
battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal
levels.
The 3.3V device is fully accessible and data can be written and read only when VCC is greater than VPF.
When VCC falls below VPF, access to the device is inhibited. If VPF is less than VSO, the device power is
switched from VCC to the internal backup lithium battery when VCC drops below VPF. If VPF is greater
than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
below VSO. RTC operation and SRAM data are maintained from the battery until VCC is returned to
nominal levels.
All control, data, and address signals must be powered down when VCC is powered down.
BATTERY LONGEVITY
The DS1553 has a lithium power source that is designed to provide energy for the clock activity and
clock and RAM data retention when the VCC supply is not present. The capability of this internal power
supply is sufficient to power the DS1553 continuously for the life of the equipment in which it is
installed. For specification purposes, the life expectancy is 10 years at +25C with the internal clock
oscillator running in the absence of VCC. Each DS1553 is shipped from Dallas Semiconductor with its
lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a
level greater than VPF, the lithium energy source is enabled for battery backup operation.
INTERNAL BATTERY MONITOR
The DS1553 constantly monitors the battery voltage of the internal battery. The Battery Low Flag (BLF)
bit of the Flags register (B4 of 1FF0h) is not writeable and should always be 0 when read. If a 1 is ever
present, an exhausted lithium energy source is indicated, and both the contents of the RTC and RAM are
questionable.
POWER-ON RESET
A temperature-compensated comparator circuit monitors the VCC level. When VCC falls to the power-fail
trip point, the RST signal (open drain) is pulled low. When VCC returns to nominal levels, the RSTsignal
continues to be pulled low for 40ms to 200ms. The power-on reset function is independent of the RTC
oscillator and is therefore operational whether or not the oscillator is enabled.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
CLOCK OPERATIONS
Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions.
Table 2. Register Map
DATA ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 FUNCTION/RANGE
1FFFh 10 Year Year Year 00-99
1FFEh X X X 10 M Month Month 01-12
1FFDh X X 10 Date Date Date 01-31
1FFCh X FT X X X Day Day 01-07
1FFBh X X 10 Hour Hour Hour 00-23
1FFAh X 10 Minutes Minutes Minutes 00-59
1FF9h OSC 10 Seconds Seconds Seconds 00-59
1FF8h W R 10 Century Century Control 00-39
1FF7h WDS BMBBMB3 BMB2BMB
BMBRB0Watchdog
1FF6h AE Y ABE Y Y Y Y Y Interrupts
1FF5h AM4 Y 10 Date Date Alarm Date 01-31
1FF4h AM3 Y 10 Hours Hours Alarm Hours 00-23
1FF3h AM2 10 Minutes Minutes Alarm Minutes 00-59
1FF2h AM1 10 Seconds Seconds Alarm Seconds 00-59
1FF1h Y Y Y Y Y Y Y Y Unused —
1FF0h WF AF 0 BLF 0 0 0 0 Flags —
X = Unused, Read/Writable Under Write and Read Bit Control AE = Alarm Flag Enable
FT = Frequency Test Bit Y = Unused, Read/Writable Without Write and Read Bit Control
OSC = Oscillator Start/Stop Bit ABE = Alarm in Battery-Backup Mode Enable
W = Write Bit AM1–AM4 = Alarm Mask Bits
R = Read Bit WF = Watchdog Flag
WDS = Watchdog Steering Bit AF = Alarm Flag
BMB0–BMB4 = Watchdog Multiplier Bits 0 = 0 Read Only
RB0–RB1 = Watchdog Resolution Bits BLF = Battery Low Flag
CLOCK OSCILLATOR CONTROL
The clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the
MSB of the Seconds register (B7 of 1FF9h). Setting it to 1 stops the oscillator; setting it to 0 starts the
oscillator. The DS1553 is shipped from Dallas Semiconductor with the clock oscillator turned off, with
the OSC bit set to 1.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
registers. This puts the external registers into a static state, allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control register (1FF8h).
As long as a 1 remains in the Control register read bit, updating is halted. After a halt is issued, the
registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
was issued. Normal updates to the external set of registers resume within 1 second after the read bit is set
to 0 for a minimum of 500s. The read bit must be 0 for a minimum of 500s to ensure the external
registers are updated.
SETTING THE CLOCK
The 8th bit, B7 of the Control register, is the write bit. Setting the write bit to 1, like the read bit, halts
updates to the DS1553 (1FF8h–1FFFh) registers. After setting the write bit to 1, RTC registers can be
loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to 0
then transfers the values written to the internal RTC registers and allows normal operation to resume.
CLOCK ACCURACY (DIP MODULE)
The DS1553 is guaranteed to keep time accuracy to within 1 minute per month at +25C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. The electrical environment also affects clock accuracy and caution should be taken to place the
RTC in the lowest level EMI section of the PC board layout. For additional information, refer to
Application Note 58: Crystal Considerations with Dallas Real-Time Clocks, available on our website at
/appnoteindex.com.
CLOCK ACCURACY (PowerCap MODULE)
The DS1553 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module typically keeps time accuracy to within 1.53 minutes per month (35ppm) at +25°C. The
electrical environment affects clock accuracy and caution should be taken to place the RTC in the lowest
level EMI section of the PC board layout. For additional information, refer to Application Note 58:
Crystal Considerations with Dallas Real-Time Clocks, available on our website at
/appnoteindex.com.
FREQUENCY TEST MODE
The DS1553 frequency test mode uses the open-drain IRQ/FT output. With the oscillator running, the
IRQ/FT output toggles at 512Hz when the FT bit is 1, the Alarm Flag Enable bit (AE) is 0, and the
Watchdog Steering bit (WDS) is 1 or the Watchdog register is reset (Register 1FF7h = 00h). The IRQ/FT
output and the frequency test mode can be used as a measure of the actual frequency of the 32.768kHz
RTC oscillator. The IRQ/FT pin is an open-drain output that requires a pullup resistor for proper
operation. The FT bit is cleared to 0 on power-up.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
USING THE CLOCK ALARM
The alarm settings and control for the DS1553 reside within registers 1FF2h–1FF5h. Register 1FF6h
contains two alarm-enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE and
ABE bits must be set as described below for the IRQ/FT output to be activated for a matched alarm
condition.
The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,
minute, or second. It can also be programmed to go off while the DS1553 is in the battery-backed state of
operation to serve as a system wakeup. Alarm mask bits AM1–AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in the table default to the once-per-second mode to
notify the user of an incorrect alarm setting.
Table 3. Alarm Mask Bits
AM4 AM3 AM2 AM1 ALARM RATE
1 1 1 1 Once per second
1 1 1 0 When seconds match 1 0 0 When minutes and seconds match
1 0 0 0 When hours, minutes, and seconds match 0 0 0 When date, hours, minutes, and seconds match
When the RTC register values match Alarm register settings, the Alarm Flag bit (AF) is set to 1. If the
Alarm Flag Enable (AE) is also set to 1, the alarm condition activates the IRQ/FT pin. The IRQ/FT signal
is cleared by a read or write to the Flags register (Address 1FF0h) as shown in Figures 2 and 3. When CE
is active, the IRQ/FT signal may be cleared by having the address stable for as short as 15ns and either or WE active, but it is not guaranteed to be cleared unless tRC is fulfilled. The alarm flag is also
cleared by a read or write to the Flags register, but the flag does not change states until the end of the
read/write cycle and the IRQ/FT signal has been cleared.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
Figure 2. Clearing IRQ Waveforms
Figure 3. Clearing IRQ Waveforms
The IRQ/FT pin can also be activated in the battery-backed mode. The IRQ/FT goes low if an alarm
occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,
however, an alarm generated during power-up sets AF. Therefore, the AF bit can be read after system
power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm
timing during the battery-backup mode and power-up states.
Figure 4. Backup Mode Alarm Waveforms
CE = Ø
CE,
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
USING THE WATCHDOG TIMER
The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog
timer by setting the desired amount of timeout into the 8-bit Watchdog register (Address 1FF7h). The five
Watchdog register bits BMB4–BMB0 store a binary multiplier and the two lower-order bits
RB1–RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and
11 = 4 seconds. The watchdog timeout value is then determined by the multiplication of the 5-bit
multiplier value with the 2-bit resolution value. (For example: writing 00001110 in the Watchdog register
= 3 x 1 second or 3 seconds.) If the processor does not reset the timer within the specified period, the
Watchdog Flag (WF) is set and a processor interrupt is generated and stays active until either the
Watchdog Flag (WF) is read or the Watchdog register (1FF7) is read or written.
The most significant bit of the Watchdog register is the Watchdog Steering Bit (WDS). When set to 0, the
watchdog activates the IRQ/FT output when the watchdog times out.
When WDS is set to 1, the watchdog outputs a negative pulse on the RSToutput for 40ms to 200ms. The
Watchdog register (1FF7) and the FT bit are reset to 0 at the end of a watchdog timeout when the WDS
bit is set to 1.
The watchdog timer resets when the processor performs a read or write of the Watchdog register. The
timeout period then starts over. Writing a value of 00h to the Watchdog register disables the watchdog
timer. The watchdog function is automatically disabled upon power-up and the Watchdog register is
cleared. If the watchdog function is set to output to the IRQ/FT output and the frequency test function is
activated, the watchdog function prevails and the frequency test function is denied.
POWER-ON DEFAULT STATES
Upon application of power to the device, the following register bits are set to 0:
WDS = 0, BMB0–BMB4 = 0, RB0–RB1 = 0, AE = 0, and ABE = 0.
