DS1543 Fast Delivery |IC PHOENIX CO.,LIMITED

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DTC144WS , DTA/DTC SERIES
DTC314TS , Digital transistors (built-in resistor)
DTC314TU , Digital transistors (built-in resistor)
DTC323TS , Digital transistors (built-in resistor)
DTC323-TS , Digital transistors (built-in resistor)
DTC343TS , Digital transistors (built-in resistor)

DS1543
64K NV Real Time Clocks RAM
FEATURESIntegrated NV SRAM, real time clock, crystal,
power-fail control circuit and lithium energy
sourceClock registers are accessed identical to the
static RAM. These registers are resident in the
sixteen top RAM locationsTotally nonvolatile with over 10 years of
operation in the absence of powerPrecision Power-On ResetProgrammable Watchdog Timer and RTC
AlarmBCD coded year, month, date, day, hours,
minutes, and seconds with automatic leap year
compensation valid up to the year 2100Battery voltage level indicator flagPower-fail write protection allows for ±10%
Vcc power supply toleranceLithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
ORDERING INFORMATION
DS1543-XXX(5V)
-70 70 ns access
-100 100 ns access
*DS1543W-XXX(3.3V)
-120 120 ns access
-150150 ns access
PIN ASSIGNMENT
PIN DESCRIPTION
A0-A12 - Address Input
DQ0-DQ7 - Data Input/Outputs
IRQ\FT - Interrupt, Frequency Test
Output (Open-Drain)
RST - Power-On Reset Output
(Open-Drain) - Chip Enable - Output Enable - Write Enable
VCC- Power Supply Input
GND - Ground
NC - No Connection
DS1543
64k NV Timekeeping RAM
VCC
IRQ/FT
DQ7
DQ6
DQ5
DQ4
DQ3
RST
A12
DQ0
DQ1
DQ2
GND
28-Pin Encapsulated Package
DS1543
DESCRIPTION
The DS1543 is a full-function real-time clock/calendar (RTC) with a RTC alarm, watchdog timer, power-
on reset, battery monitor, and 8k x 8 non-volatile static RAM. User access to all registers within the
DS1543 is accomplished with a bytewide interface as shown in Figure 1. The RTC registers contain year,
month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for day of month
and leap year are made automatically.
The RTC registers are double-buffered into an internal and external set. The user has direct access to the
external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow
the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers are
continuously updated; this occurs regardless of external registers settings to guarantee that accurate RTCinformation is always maintained.
The DS1543 has interrupt (IRQ/FT) and reset (RST) outputs which can be used to control CPU activity.
The IRQ/FT interrupt output can be used to generate an external interrupt when the RTC register values
match user programmed alarm values. The interrupt is always available while the device is powered from
the system supply and can be programmed to occur when in the battery backed state to serve as a system
wake-up. Either the IRQ/FT or RST outputs can also be used as a CPU watchdog timer, CPU activity is
monitored and an interrupt or reset output will be activated if the correct activity is not detected withinprogrammed limits. The DS1543 power-on reset can be used to detect a system power down or failure
and hold the CPU in a safe reset state until normal power returns and stabilizes; the RST output is used
for this function.
The DS1543 also contains its own power fail circuitry which automatically deselects the device when the
VCC supply enters an out of tolerance condition. This feature provides a high degree of data securityduring unpredictable system operation brought on by low VCC levels.
PACKAGES
The DS1543 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)that contains the crystal and battery. This design allows the Power-Cap to be mounted on top of the
DS1543P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module board and
PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCapis DS9034PCX.
DS1543
DS1543 BLOCK DIAGRAM Figure 1
DS1543 OPERATING MODES Table 1
DATA READ MODE
The DS1543 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple through access to any valid address location. Valid data will be
available at the DQ pins within tAA after the last address input is stable, providing that CE and OE access
times are satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip
enable access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is
controlled by CE and OE. If the outputs are activated before tAA, the data lines are driven to an
intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data
will remain valid for output data hold time (tOH) but will then go indeterminate until the next address
access.
DATA WRITE MODE
The DS1543 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout
the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent
DS1543
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WEtransitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
The 5-volt device is fully accessible and data can be written and read only when VCC is greater than VPF.
However, when VCC is below the power-fail point VPF (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switchpoint VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium
battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal
levels.
The 3.3-volt device is fully accessible and data can be written and read only when VCC is greater thanVPF. When VCC falls below VPF, access to the device is inhibited. If VPF is less than VBAT, the device
power is switched from VCC to the internal backup lithium battery when VCC drops below VPF If VPF is
greater than VBAT, the device power is switched from VCC to the internal backup lithium battery when
VCC drops below VBAT. RTC operation and SRAM data are maintained from the battery until VCC is
returned to nominal levels.
All control, data, and address signals must be powered down when VCC is powered down.
BATTERY LONGEVITY
The DS1543 has a lithium power source that is designed to provide energy for the clock activity, and
clock and RAM data retention when the VCC supply is not present. The capability of this internal powersupply is sufficient to power the DS1543 continuously for the life of the equipment in which it is
installed. For specification purposes, the life expectancy is 10 years at 25°C with the internal clock
oscillator running in the absence of VCC Each DS1543 is shipped from Dallas Semiconductor with its
lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a
level greater than VPF the lithium energy source is enabled for battery backup operation. Actual lifeexpectancy of the DS1543 will be much longer than 10 years since no internal battery energy is
consumed when VCC is present. In fact, in most applications, the life expectancy of the DS1543 will be
approximately equal to the shelf life (expected useful life of the internal lithium battery with no load
attached) of the battery which may prove to be as long as 20 years.
INTERNAL BATTERY MONITORThe DS15433 constantly monitors the battery voltage of the internal batter. The Battery Low Flag (BLF)
bit of the Flags register (B4 of 1FF0h) is not writable and should always be a 0 when read. If a 1 is ever
present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are
questionable.
POWER-ON RESET
A temperature-compensated comparator circuit monitors the level of VCC When VCC falls to the power
fail trip point, the RST signal (open-drain) is pulled low. When VCC returns to nominal levels, the RSTsignal continues to be pulled low for a period of 40 ms to 200 ms. The power-on reset function is
independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.
DS1543
DS1543 REGISTER MAP Table 2FUNCTION/RANGE10 Year
X = Unused, read/writable under Write and ReadAE = Alarm Flag Enable
bit controlY = Unused, read/writable without Write andFT = Frequency Test bitbit control
OSC = Oscillator start/stop bitABE = Alarm in battery Back-up mode enable
W = Write bitAM1-AM4 = Alarm Mask bits
R = Read bitWF = Watchdog Flag
WDS = Watchdog Steering bitAF = Alarm FlagBMB0-BMB4 = Watchdog Multiplier bits0 = “0” and are read only
RB0-RB1 = Watchdog Resolution bitsBLF = Battery Low Flag
CLOCK OSCILLATOR CONTROL
The Clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the
MSB of the seconds register (B7 of 1FF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the
oscillator. The DS1543 is shipped from Dallas Semiconductor with the clock oscillator turned off, OSC
bit set to a 1.
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
registers. This puts the external registers into a static state allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control register (1FF8h).As long as a 1 remains in the Control register read bit, updating is halted. After a halt is issued, the
registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
was issued. Normal updates to the external set of registers will resume within 1 second after the read bit
DS1543
SETTING THE CLOCK
The 8th bit, B7 of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts
updates to the DS1543 (1FF8h-1FFFh) registers. After setting the write bit to a 1, RTC registers can be
loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to
a 0 then transfers the values written to the internal RTC registers and allows normal operation to resume.
CLOCK ACCURACY (DIP MODULE)
The DS1543 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements. The DS1543 does
not require additional calibration and, in most applications, temperature deviations will have a negligible
effect on accuracy. For this reason, methods of field clock calibration are not available and not necessary.
Attempts to calibrate the RTC that may be used with similar device types (M48T5x family) will not haveany effect even though the DS1543 appears to accept calibration data.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1543 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C.
FREQUENCY TEST MODE
The DS1543 frequency test mode uses the open-drain IRQ/FT output. With the oscillator running, the
IRQ/FT output will toggle at 512 Hz when the FT bit is a 1, the Alarm Flag Enable bit (AE) is a 0, and
the Watchdog Steering bit (WDS) is a 1 or the Watchdog Register is reset (register 1FF7h = 00h). The
IRQ/FT output and the frequency test mode can be used as a measure of the actual frequency of the
32.768 kHz RTC oscillator. The IRQ/FT pin is an open-drain output which requires a pullup resistor for
proper operation. The FT bit is cleared to a 0 on power-up.
USING THE CLOCK ALARM
The alarm settings and control for the DS1543 reside within registers 1FF2h - 1FF5h. Register 1FF6h
contains two alarm enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE and
ABE bits must be set as described below for the IRQ/FT output to be activated for a matched alarm
condition.
The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,
minute, or second. It can also be programmed to go off while the DS1543 is in the battery-backed state of
operation to serve as a system wake-up. Alarm mask bits AM1-AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in the table default to the once per second mode tonotify the user of an incorrect alarm setting.
ALARM MASK BITS Table 3
DS1543
When the RTC register values match alarm register settings, the Alarm Flag bit (AF) is set to a 1. If
Alarm Flag Enable (AE) is also set to a 1, the alarm condition activates the IRQ/FT pin. The IRQ/FT
signal is cleared by a read or write to the Flags register (Address 1FF0h) as shown in Figure 2. The
IRQ/FT signal may be cleared by having the address stable for as short as 15 ns and either CE or WE
active, but is not guaranteed to be cleared unless tRC is fulfilled. The alarm flag is also cleared by a read
or write to the Flags register, but the flag will not change states until the end of the read/write cycle and
the IRQ/FT signal has been cleared.
CLEARING IRQ WAVEFORMS Figure 2
CLEARING IRQ WAVEFORMS Figure 3
The IRQ/FT pin can also be activated in the battery-backed mode. The IRQ/FT will go low if an alarm
occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,
however an alarm generated during power-up will set AF. Therefore the AF bit can be read after system
power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates
alarm timing during the battery backup mode and power-up states.
DS1543
BACK-UP MODE ALARM WAVEFORMS Figure 4
USING THE WATCHDOG TIMER
The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog
timer by setting the desired amount of time-out into the 8-bit Watchdog Register (Address 1FF7h). Thefive Watchdog Register bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-
RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The
watchdog time-out value is then determined by the multiplication of the 5-bit multiplier value with the 2-
bit resolution value. (For example: writing 00001110 in the watchdog Register = 3 X 1 second or 3
seconds). If the processor does not reset the timer within the specified period, the Watchdog Flag (WF) isset and a processor interrupt is generated and stays active until either the Watchdog Flag (WF) is read or
the watchdog register (1FF7) is read or written.
The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a 0,
the watchdog will activate the IRQ/FT output when the watchdog times out.
When WDS is set to a 1, the watchdog will output a negative pulse on the RST output for a duration of40 ms to 200 ms. The Watchdog register (1FF7) and the FT bit will reset to a 0 at the end of a watchdog
time-out when the WDS bit is set to a 1.
The watchdog timer resets when the processor performs a read or write of the Watchdog register. The
time-out period then starts over. The watchdog timer is disabled by writing a value of 00h to thewatchdog register. The watchdog function is automatically disabled upon power-up and the Watchdog
register is cleared. If the watchdog function is set to output to the IRQ/FT output and the frequency test
function is activated, the watchdog function prevails and the frequency test function is denied.
POWER-ON DEFAULT STATES
Upon application of power to the device, the following register bits are set to 0:
WDS=0, BMB0-BMB4=0, RB0-RB1=0, AE=0, ABE=0.
DS1543
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -5.0V to +6.0V
Operating Temperature 0°C to 70°C
Storage Temperature -55°C to +125°C
Soldering Temperature 260°C for 10 seconds (DIP Package) (See Note 8)See IPC/JEDEC Standard J-STD-020A for
Surface Mount Devices
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
RECOMMENDED DC OPERATING CONDITIONS (Over the Operating Range)
DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)

Partno	Mfg	Dc	Qty	Available	Descript
DS1543	DALLAS	N/a	15	avai	64K NV Real Time Clocks RAM