DS1501WE+ ,Y2K-Compliant Watchdog Real-Time ClocksAPPLICATIONS 256 Bytes Battery-Backed SRAM Remote Systems Auxiliary Battery Input Battery-Backe ..
DS1501WEN ,Y2K-Compliant Watchdog Real-Time ClocksFEATURES The DS1501/DS1511 are full-function, year 2000- BCD-Coded Century, Year, Month, Date, D ..
DS1501WS ,Y2K-Compliant Watchdog Real-Time ClocksAPPLICATIONS 256 Bytes Battery-Backed SRAM Remote Systems Auxiliary Battery Input Battery-Backe ..
DS1501WS ,Y2K-Compliant Watchdog Real-Time ClocksELECTRICAL CHARACTERISTICS (DS1511: V = 3.3V or 5V ±10%, T = 0°C to +70°C; DS1501: V = 3.3V or 5V ± ..
DS1501WSN ,Y2K-Compliant Watchdog Real-Time ClocksELECTRICAL CHARACTERISTICS (V = 3.3V or 5V ±10%, T = 0°C to +70°C; V = 3.3V or 5V ±10%, T = -40°C t ..
DS1501YE ,Y2K-Compliant Watchdog Real-Time ClocksELECTRICAL CHARACTERISTICS (DS1511: V = 3.3V or 5V ±10%, T = 0°C to +70°C; DS1501: V = 3.3V or 5V ± ..
DTC144VKA-T146 , Only the on/off conditions need to be set for operation, making the circuit design easy.
DTC144VUA , 100mA / 50V Digital transistor (with built-in resistors)
DTC144WE ,Bias Resistor TransistorDTC114EET1 SeriesBias Resistor TransistorNPN Silicon Surface Mount Transistorwith Monolithic Bias R ..
DTC144WET1 ,Bias Resistor TransistorFeatures(OUTPUT)PIN 1R1• Simplifies Circuit DesignBASE(INPUT)• Reduces Board SpaceR2• Reduces Compo ..
DTC144WS , DTA/DTC SERIES
DTC314TS , Digital transistors (built-in resistor)
DS1501W+-DS1501WE-DS1501WE+-DS1501WS-DS1501YE-DS1511W+-DS1511Y+
Y2K-Compliant Watchdog Real-Time Clocks
GENERAL DESCRIPTION The DS1501/DS1511 are full-function, year 2000-compliant real-time clock/calendars (RTCs) with an RTC alarm, watchdog timer, power-on reset, battery monitors, 256 bytes NV SRAM, and a 32.768kHz output. User access to all registers within the DS1501/DS1511 is accomplished with a byte-wide interface, as shown in Figure 8. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for day of month and leap year are made automatically.
APPLICATIONS Remote Systems Battery-Backed Systems Telecom Switches Office Equipment Consumer Electronics Pin Configurations and Typical Operating Circuit appear at end of data sheet.
FEATURES
BCD-Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap-Year Compensation Valid Up to the Year 2100
Programmable Watchdog Timer and RTC Alarm
Century Register; Y2K-Compliant RTC
+3.3 (W) or +5V (Y) Operation
Precision Power-On Reset
Power-Control Circuitry Support System Power-On from Date/Day/Time Alarm or Key Closure/Modem-Detect Signal
256 Bytes Battery-Backed SRAM
Auxiliary Battery Input
Accuracy of DS1511 Better than ±1 Minute/Month at +25°C
Day-of-Week/Date Alarm Register
Crystal Select Bit Allow RTC to Operate with 6pF or 12.6pF Crystal (DS1501)
Battery Voltage-Level Indicator Flags
Available as Chip (DS1501) or Stand-Alone Encapsulated DIP Module with Embedded Battery and Crystal (DS1511)
Underwriters Laboratories (UL) Recognized ORDERING INFORMATION
PART VOLTAGE (V) TEMP RANGE PIN-PACKAGE TOP MARK* DS1501WE+ 3.3 0°C to +70°C 28 TSOP DS1501WE DS1501WEN+ 3.3 -40°C to +85°C 28 TSOP DS1501WEN DS1501WEN+T&R 3.3 -40°C to +85°C 28 TSOP DS1501WEN DS1501WE+T&R 3.3 0°C to +70°C 28 TSOP DS1501WE
+Denotes a lead(Pb)-free/RoHS-compliant package. *A “+” anywhere on the top mark denotes a lead(Pb)-free device. An N or IND denotes an industrial temperature device. T&R = Tape and reel.
Ordering Information continued at end of data sheet.
DS1501/DS1511 Y2K-Compliant Watchdog Real-Time Clocks
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground….…………………………………………………..……....-0.5V to +6.0V Operating Temperature Range DS1501………………………………………………………….………………………………….-40°C to +85°C (Note 1) DS1511……………………………………………………………….………………………………………...0°C to +70°C Storage Temperature Range DS1501…………………...………………………………………………………………………………...-55°C to +125°C DS1511………………………………………………………………….…………………………………....-40°C to +70°C Lead Temperature (soldering, 10 seconds)…..………...………………………………………...……..…………..+260°C Note: EDIP is hand or wave-soldered only. (Note 2) Soldering Temperature (reflow, SO or TSOP)…….………….….......................................................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS (DS1511: VCC = 3.3V or 5V ±10%, TA = 0°C to +70°C; DS1501: VCC = 3.3V or 5V ±10%, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power Supply Voltage (Note 3) VCC 5V (Y) 4.5 5.0 5.5 V 3.3V (W) 3.0 3.3 3.6
Logic 1 Voltage All Inputs (Note 3) VIH Y 2.2 VCC + 0.3 V W 2.0 VCC + 0.3 Pullup Voltage, IRQ, PWR, and
RST Outputs (Note 3) VPU 5.5 V
Logic 0 Voltage All Inputs (Note 3) VIL Y -0.3 +0.8 V W -0.3 +0.6
Battery Voltage (Note 3) VBAT 2.5 3.0 3.7 V
Auxiliary Battery Voltage (Note 3) VBAUX Y 2.5 3.0 5.3 V W 2.5 3.0 3.7
DC ELECTRICAL CHARACTERISTICS (DS1511: VCC = 3.3V or 5V ±10%, TA = 0°C to +70°C; DS1501: VCC = 3.3V or 5V ±10%, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Active Supply Current (Note 4) ICC Y 15 mA W 10
TTL Standby Current (CE = VIH) ICC1 Y 5 mA W 4 CMOS Standby Current (CE = VCC - 0.2V) ICC2 Y 5 mA W 4
Input Leakage Current (Any Input) IIL -1 +1 µA
Output Leakage Current (Any Output) IOL -1 +1 µA Output Logic 1 Voltage (IOUT = -1.0mA) VOH (Note 3) 2.4 V
Output Logic 0 Voltage (IOUT = 2.1mA, DQ0–7; IOUT = 5.0mA, IRQ, IOUT = 7.0mA, PWR and RST)
VOL1 (Note 3) 0.4 V
VOL2 (Notes 3, 5) 0.4 V
Battery Low, Flag Trip Point (Note 2) VBLF Y 2.0 V W 1.9
Power-Fail Voltage (Note 2) VPF Y 4.20 4.50 V W 2.75 2.97
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Battery Switchover Voltage (Notes 3, 6) VSO VBAT, VBAUX, or VPF V
Battery Leakage Current ILKG 100 nA
DC ELECTRICAL CHARACTERISTICS (DS1511: VCC = 0V; TA = 0°C to +70°C; DS1501: VCC = 0V, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Battery Current, BB32 = 0, EOSC = 0 IBAT1 (Note 7) 0.27 1.0 µA Battery Current, BB32 = 0, EOSC = 1 IBAT2 (Note 7) 0.01 0.1 µA VBAUX Current BB32 = 1, SQW Open IBAUX (Note 7) 2 µA
CRYSTAL SPECIFICATIONS*
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Nominal Frequency fO 32.768 kHz Series Resistance ESR 45 kΩ Load Capacitance CL 6/12.5 pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
AC OPERATING CHARACTERISTICS (DS1511: VCC = 5V ±10%, TA = 0°C to +70°C; DS1501: VCC = 5V ±10%, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Read Cycle Time tRC 70 ns Address Access Time tAA 70 ns
CE to DQ Low-Z tCEL (Note 8) 5 ns
CE Access Time tCEA 70 ns
CE Data-Off Time tCEZ (Note 8) 25 ns
OE to DQ Low-Z (0°C to +85°C) tOEL (Note 8) 5 ns
OE to DQ Low-Z (-40°C to 0°C) tOEL (Note 8) 2 ns
OE Access Time tOEA 35 ns
OE Data-Off Time tOEZ (Note 8) 25 ns Output Hold from Address tOH 5 ns Write Cycle Time tWC 70 ns Address Setup Time tAS 0 ns
WE Pulse Width tWEW 50 ns
CE Pulse Width tCEW 55 ns Data Setup Time tDS 30 ns Data Hold Time tDH 5 ns Address Hold Time tAH 0 ns
WE Data-Off Time tWEZ (Note 8) 25 ns Write Recovery Time tWR 15 ns Pulse Width, OE, WE, or CE High PWHIGH 20 ns Pulse Width, OE, WE, or CE Low PWLOW 70 ns
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
AC OPERATING CHARACTERISTICS (DS1511: VCC = 3.3V ±10%, TA = 0°C to +70°C; DS1501: VCC = 3.3V ±10%, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Read Cycle Time tRC 120 ns Address Access Time tAA 120 ns
CE to DQ Low-Z tCEL (Note 8) 5 ns
CE Access Time tCEA 120 ns
CE Data Off Time tCEZ (Note 8) 40 ns
OE to DQ Low-Z (0°C to +85°C) tOEL (Note 8) 5 ns
OE to DQ Low-Z (-40°C to 0°C) tOEL (Note 8) 2 ns
OE Access Time tOEA 100 ns
OE Data-Off Time tOEZ (Note 8) 35 ns Output Hold from Address tOH 5 ns Write Cycle Time tWC 120 ns Address Setup Time tAS 0 ns
WE Pulse Width tWEW 100 ns
CE Pulse Width tCEW 110 ns Data Setup Time tDS 80 ns Data Hold Time tDH 5 ns Address Hold Time tAH 5 ns
WE Data-Off Time tWEZ (Note 8) 40 ns Write Recovery Time tWR 15 ns Pulse Width, OE, WE, or CE High PWHIGH 40 ns Pulse Width, OE, WE, or CE Low PWLOW 100 ns
Figure 1. Read Cycle Timing RC CEA OEA CEL OEL OH OEZ AA
VALID DQ0-DQ7
OE
CE
A0–A4 CEZ
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
Figure 2. Write Cycle Timing, Write-Enable Controlled Figure 3. Write Cycle Timing, Chip-Enable Controlled WC AH DS AS WEZ t DH WR AS
DATA INPUT DQ0–DQ7
WE
CE
A0–A4
DATA OUTPUT DATA INPUT WEW
VALID VALID
tWC
tAH
tDS
tAS
tDH
tWR
tAS
DATA INPUTDQ0-DQ7
A0-A4
DATA INPUT
tCEW
VALIDVALID
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
Figure 4. Burst Mode Timing Waveform A0–A4
DQ0–DQ7
OE, WE, OR CE
13h
PWHIGH PWLOW
POWER-UP/DOWN CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CE or WE at VIH Before Power-Fail tPF 0 µs
VCC Fall Time: VPF(MAX) to VPF(MIN) tF 300 µs
VCC Fall Time: VPF(MIN) to VSO tFB 10 µs
VCC Rise Time: VPF(MIN) to VPF(MAX) tR 0 µs
VPF to RST High tREC 35 200 ms (TA = +25°C)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Expected Data-Retention Time (Oscillator On) tDR (Note 9) 10 Years
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Capacitance on All Input Pins CIN 10 pF
Capacitance on IRQ, PWR, RST, and DQ Pins CIO 10 pF
AC TEST CONDITIONS
OUTPUT LOAD INPUT PULSE LEVELS TIMING MEASUREMENT REFERENCE LEVELS INPUT PULSE RISE AND FALL TIMES (Y) 50pF + 1TTL Gate 0V to 3.0V for 5V operation Input: 1.5V 5ns (W) 25pF + 1 TTL Gate Output: 1.5V
OE, WE, or CE
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
Figure 5. 3.3V Power-Up/Down Waveform Timing
Figure 6. 5V Power-Up/Down Waveform Timing Warning: Under no circumstances are negative undershoots, of any amplitude, allowed when
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
WAKEUP/KICKSTART TIMING
(TA = +25°C) (Figure 7)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Kickstart-Input Pulse Width tKSPW 2 µs
Wakeup/Kickstart Power-On Timeout tPOTO (Note 10) 2 s Note: Time intervals shown above are referenced in Wakeup/Kickstart. Figure 7. Wakeup/Kickstart Timing Diagram
tKSPW
tPOTO
VCC
CONDITION:VPFVBATVBAT
VBAT
VPFVCC
CONDITION:
VBATVPF>
TDF/KSF(INTERNAL)
VIL
VIH
HI-Z____IRQ
VIL
VIH
HI-Z____PWR
VIH
VIL
___KS2345INTERVALS Note 1: Limits at -40°C are not production tested and are guaranteed by design. Note 2: RTC modules can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post-solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not used to prevent damage to the crystal.
Note 3: Voltage referenced to ground. Note 4: Outputs are open. Note 5: The IRQ, PWR, and RST outputs are open drain. Note 6: If VPF is less than VBAT and VBAUX, the device power is switched from VCC to the greater of VBAT or VBAUX when VCC drops below VPF. If VPF is greater than VBAT and VBAUX, the device power is switched from VCC to the greater of VBAT or VBAUX when VCC drops below the greater of VBAT or VBAUX.
Note 7: VBAT or VBAUX current. Using a 32,768Hz crystal connected to X1 and X2. Note 8: These parameters are sampled with a 5pF load and are not 100% tested. Note 9: tDR is the amount of time that the internal battery can power the internal oscillator and internal registers of the DS1511. Note 10: If the oscillator is not enabled, the startup time of the oscillator after VCC1 is applied will be added to the wakeup/kickstart timeout.
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
PIN DESCRIPTION
PIN NAME FUNCTION SO EDIP TSOP 1 8 PWR Active-Low Power-On Output (Open Drain). This output, if used, is normally connected to power-supply control circuitry. This pin requires a pullup resistor connected to a positive supply to operate correctly.
2, 3 — 9, 10 X1, X2
Connections for Standard 32.768kHz Quartz Crystal. For greatest accuracy, the DS1501 must be used with a crystal that has a specified load capacitance of either 6pF or 12.5pF. The crystal select (CS) bit in control register B is used to select operation with a 6pF or 12.5pF crystal. The crystal is attached directly to the X1 and X2 pins. There is no need for external capacitors or resistors. An external 32.768kHz oscillator can also drive the DS1501. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. See Figure 9. An enable bit in the month register controls the oscillator. Oscillator startup time is highly dependent upon crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with the recommended characteristics and proper layout usually starts within one second. 4 11 RST
Active-Low Reset Output. (Open Drain). This output, if used, is normally connected to a microprocessor-reset input. This pin requires a pull up resistor connected to a positive supply to operate correctly. When RST is active, the device is not accessible. 5 12 IRQ Active-Low Interrupt Output (Open Drain). This output, if used, is normally connected to a microprocessor interrupt input. This pin requires a pullup resistor connected to a positive supply to operate correctly.
6–10 6–10 13–17 A4–A0 Address Inputs. Selects one of 17 register locations.
11–13, 15–19 11–13, 15–19 18–20, 22–26 DQ0–DQ7 Data Input/Output. I/O pins for 8-bit parallel data transfer.
14, 21 14 21, 28 GND
Ground. DC power is applied to the device on these pins. VCC is the positive terminal. When power is applied within the normal limits, the device is fully accessible and data can be written and read. When VCC drops below the normal limits, reads and writes are inhibited. As VCC drops below the battery voltage, the RAM and timekeeping circuits are switched over to the battery.
22 22 1 OE Output-Enable Input. Active-low input that enables DQ0–DQ7 for data output from the device.
20 20 27 CE Chip-Enable Input. Active-low input to enable the device.
23 23 2 SQW Square-Wave Output. When enabled, the SQW pin outputs a 32.768kHz square wave. If the square wave (E32K) and battery backup 32kHz (BB32) bits are enabled, power is provided by VBAUX when VCC is absent.
24 24 3 KS Active-Low Kickstart Input. This pin is used to wake up a system from an external event, such as a key closure. The KS pin is normally connected using a pullup resistor to VBAUX. If the KS function is not used, connect to ground.
25 — 4 VBAT
Battery Input for Any Standard 3V Lithium Cell or Other Energy Source. Battery voltage must be held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse charging current when used with a lithium battery. www.maximintegrated.com/TechSupport/QA/ntrl.htm If not used, connect to ground.
26 26 5 VBAUX
Auxiliary Battery Input for Any Standard 3V Lithium Cell or Other Energy Source. Battery voltage must be held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse charging current when used with a lithium battery, www.maximintegrated.com/TechSupport/QA/ntrl.htm. If not used, connect to ground.
27 27 6 WE Write-Enable Input. Active-low input that enables DQ0–DQ7 for data input to the device.
28 28 7 VCC
DC Power. VCC is the positive terminal. When power is applied within the normal limits, the device is fully accessible and data can be written and read. When VCC drops below the normal limits, reads and writes are inhibited. As VCC drops below the battery voltage, the RAM and timekeeping circuits are switched over to the battery. 2, 3, 21,
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
Figure 8. Block Diagram Figure 9. Typical Crystal Layout
CRYSTAL
X1
X2
GND
LOCAL GROUND PLANE (LAYER 2)
RST
PWR
256 x 8 NV SRAM
POWER CONTROL WRITE PROTECTION, AND POWER-ON RESET
16 X 8
CLOCK AND CONTROL REGISTERS BAT BAT BAUX
GND
KS
A0–A4
DQ0–DQ7
CE
WE
OE
X1
X2
32.768kHz CLOCK OSCILLATOR
IRQ
SQW
CLOCK ALARM AND WATCHDOG COUNTDOWN
DS1501/DS1511
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
DETAILED DESCRIPTION
The DS1501/DS1511 RTC is a low-power clock/date device with a programmable day of week/date alarm. The DS1501/DS1511 is accessed through a parallel interface. The clock/date provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year.
The RTC registers are double buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. When the crystal oscillator is turned on, the internal set of registers are continuously updated; this occurs regardless of external register settings to guarantee that accurate RTC information is always maintained.
The DS1501/DS1511 contain their own power-fail circuitry that automatically deselects the device when the VCC supply falls below a power-fail trip point. This feature provides a high degree of data security during unpredictable system operation caused by low VCC levels.
The DS1501/DS1511 have interrupt (IRQ), power control (PWR), and reset (RST) outputs that can be used to control CPU activity. The IRQ interrupt or RST outputs can be invoked as the result of a time-of-day alarm, CPU watchdog alarm, or a kickstart signal. The DS1501/DS1511 power-control circuitry allow the system to be powered on by an external stimulus, such as a keyboard or by a time and date (wakeup) alarm. The PWR output pin can be triggered by one or either of these events, and can be used to turn on an external power supply. The PWR pin is under software control, so that when a task is complete, the system power can then be shut down. The DS1501/DS1511 power-on reset can be used to detect a system power-down or failure and hold the CPU in a safe reset state until normal power returns and stabilizes; the RST output is used for this function.
The DS1501/DS1511 are clock/calendar chips with the features described above. An external crystal and battery are the only components required to maintain time-of-day and memory status in the absence of power.
Table 1. RTC Operating Modes
VCC CE OE WE DQ0–DQ7 A0–A4 MODE POWER
In tolerance IH X X High-Z X Deselect Standby IL X VIL DIN AIN Write Active IL VIL VIH DOUT AIN Read Active IL VIH VIH High-Z AIN Read Active
VSO < VCC < VPF X X X High-Z X Deselect CMOS Standby
VCC < VSO < VPF X X X High-Z X Data Retention Battery Current DATA READ MODE
The DS1501/DS1511 are in read mode whenever CE (chip enable) and OE (output enable) are low and WE (write enable) is high. The device architecture allows ripple-through access to any valid address location. Valid data is available at the DQ pins within tAA (address access) after the last address input is stable, provided that CE and OE
access times are satisfied. If CE or OE access times are not met, valid data is available at the latter of chip-enable access (tCSA) or at output-enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE
and OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data remains valid for output-data hold time (tOH)
but then goes indeterminate until the next address access (Table 1). DATA WRITE MODE
The DS1501/DS1511 are in write mode whenever CE and WE are in their active state. The start of a write is referenced to the latter occurring transition of CE or WE. The addresses must be held valid throughout the cycle.
CE or WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read or write cycle. Data
in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to a high-to-low transition on WE, the data bus can become active with read data
