DS1486-120 ,RAMified Watchdog TimekeeperDS1486/DS1486PRAMified Watchdog Timekeeper
DS1486-120 ,RAMified Watchdog TimekeeperFEATURES PIN ASSIGNMENT 128 kbytes of user NV RAMINTB (INTB)1 32 VCC Integrated NV SRAM, real-tim ..
DS1486-120+ ,RAMified Watchdog TimekeeperFEATURES ORDERING INFORMATION TEMP PIN- TOP 128 kbytes of User NV RAM PART RANGE PACKAGE MARK* ..
DS1486P-120 ,RAMified Watchdog TimekeeperFEATURES PIN ASSIGNMENT 128 kbytes of user NV RAMINTB (INTB)1 32 VCC Integrated NV SRAM, real-tim ..
DS1486P-120+ ,RAMified Watchdog TimekeeperFEATURES ORDERING INFORMATION TEMP PIN- TOP 128 kbytes of User NV RAM PART RANGE PACKAGE MARK* ..
DS1487 ,Low Power RS-485 1/4 Unit Load Multipoint TransceiverElectrical CharacteristicsOver Supply Voltage and Operating Temperature Ranges, unless otherwise sp ..
DTC143ZKA T146 , NPN 100mA 50V Digital Transistors
DTC143ZKA T146 , NPN 100mA 50V Digital Transistors
DTC143ZKAT146 , NPN 100mA 50V Digital Transistors
DTC143ZKAT146 , NPN 100mA 50V Digital Transistors
DTC143ZKA-T146 , NPN 100mA 50V Digital Transistors
DTC143ZM3T5G ,Bias Resistor TransistorELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted, common for Q and Q )A 1 2Characteristi ..
DS1486-120-DS1486P-120
RAMified Watchdog Timekeeper
FEATURES128 kbytes of user NV RAMIntegrated NV SRAM, real-time clock,
crystal, power-fail control circuit and lithium
energy sourceTotally nonvolatile with over 10 years of
operation in the absence of powerWatchdog timer restarts an out-of-control
processorAlarm function schedules real-time relatedactivities such as system wakeupProgrammable interrupts and square wave
outputAll registers are individually addressable via
the address and data busInterrupt signals active in power-down mode
ORDERING INFORMATIONDS1486XXX(32–pin DIP module)–150150 ns access
–120120 ns access
*DS1486PXXX34-pin PowerCap Module Board
–150150 ns access
–120120 ns access
*DS9034PCX PowerCap Required (must be ordered separately)
PIN DESCRIPTIONINTB – Interrupt Output A (open drain)
INTB (INTB)– Interrupt Output B (open drain)
A0–A16 – Address Inputs
DQ0–DQ7 – Data Input/Output – Chip Enable – Output Enable – Write Enable
VCC – +5 VoltsGND – Ground
SQW – Square Wave Output
PIN ASSIGNMENT
DS1486/DS1486PA15A16PFOVCC WEOECEDQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0GND
INTA
34-Pin PowerCap Module Board
(Uses DS9034PCX PowerCap)
DS1486 128k x 8
32-Pin Encapsulated Package
A14
DQ1
DQ0
VCC
INTA/SQW
DQ7
DQ5
DQ6
A16
A12
DQ2
GND
DQ4
DQ3
DS1486/DS1486P
DESCRIPTIONThe DS1486 is a nonvolatile Static RAM with a full function Real-time clock (RTC), alarm, watchdog
timer, and interval timer which are all accessible in a bytewide format. The DS1486 contains a lithiumenergy source and a quartz crystal which eliminate the need for any external circuitry. Data contained
within 128K by 8-bit memory and the timekeeping registers can be read or written in the same manner as
bytewide static RAM. The timekeeping registers are located in the first 14 bytes of memory space. Data
is maintained in the RAMified Timekeeper by intelligent control circuitry which detects the status of VCC
and write-protects memory when VCC is out of tolerance. The lithium energy source can maintain data andreal time for over 10 years in the absence of VCC. Timekeeper information includes hundredths of
seconds, seconds, minutes, hours, day, date, month, and year. The date at the end of the month is
automatically adjusted for months with less than 31 days, including correction for leap year. The
RAMified Timekeeper operates in either 24-hour or 12-hour format with an AM/PM indicator. The
watchdog timer provides alarm interrupts and interval timing between 0.01 seconds and 99.99 seconds.The real time alarm provides for preset times of up to one week. Interrupts for both watchdog and RTC
will operate when system is powered down. Either can provide system “wake-up” signals.
PACKAGESThe DS1486 is available in two packages: 32-pin DIP module and 34-pin PowerCap module. The 32-pin
DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 32-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap(DS90934PCX) that contains the crystal and battery. The design allows the PowerCap to be mounted on
top of the DS1486P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to high temperatures required for
solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and
PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCapis DS9034PCX.
OPERATION - READ REGISTERSThe DS1486 executes a read cycle whenever WE (Write Enable) is inactive (High), CE (Chip Enable)
and OE (Output Enable) are active (Low). The unique address specified by the address inputs (A0-A16)
defines which of the registers is to be accessed. Valid data will be available to the eight data output
drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE
access times are also satisfied. If OE and CE access times are not satisfied, then data access must be
measured from the latter occurring signal (CE or OE) and the limiting parameter is either tCO for CE or
tOE for OE rather than address access.
OPERATION - WRITE REGISTERSThe DS1486 is in the write mode whenever the WE (Write Enable) and CE (Chip Enable) signals are in
the active (Low) state after the address inputs are stable. The latter occurring falling edge of CE or WE
will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE
or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state
for a minimum recovery state (tWR) before another cycle can be initiated. Data must be valid on the data
bus with sufficient Data Set-Up (tDS) and Data Hold Time (tDH) with respect to the earlier rising edge of or WE. The OE control signal should be kept inactive (High) during write cycles to avoid bus
DS1486/DS1486P
DATA RETENTIONThe RAMified Timekeeper provides full functional capability when VCC is greater than 4.5 volts and
write-protects the register contents at 4.25 volts typical. Data is maintained in the absence of VCC without
any additional support circuitry. The DS1486 constantly monitors VCC. Should the supply voltage decay,
the RAMified Timekeeper will automatically write-protect itself and all inputs to the registers become
“don’t care.” The two interrupts INTA and INTB (INTB) and the internal clock and timers continue to run
regardless of the level of VCC. However, it is important to insure that the pull-up resistors used with theinterrupt pins are never pulled up to a value that is greater than VCC + 0.3V. As VCC falls below
approximately 3.0 volts, a power switching circuit turns the internal lithium energy source on to maintain
the clock and timer data functionality. It is also required to insure that during this time (battery backup
mode), the voltage present at INTA and INTB (INTB) never exceeds VBAT. During power-up, when VCC
rises above approximately 3.0 volts, the power switching circuit connects external VCC and disconnects
the internal lithium energy source. Normal operation can resume after VCC exceeds 4.5 volts for a periodof 200 ms.
RAMIFIED TIMEKEEPER REGISTERSThe RAMified Timekeeper has 14 registers which are 8 bits wide that contain all of the timekeeping,
alarm, watchdog and control information. The clock, calendar, alarm, and watchdog registers are memory
locations which contain external (user-accessible) and internal copies of the data. The external copies areindependent of internal functions except that they are updated periodically by the simultaneous transfer of
the incremented internal copy (see Figure 1). The Command Register bits are affected by both internal
and external functions. This register will be discussed later. Registers 0, 1, 2, 4, 6, 8, 9, and A contain
time of day and date information (see Figure 2). Time of day information is stored in BCD. Registers 3,
5, and 7 contain the Time of Day Alarm information. Time of Day Alarm information is stored in BCD.Register B is the Command Register and information in this register is binary. Registers C and D are the
Watchdog Alarm Registers and information which is stored in these two registers is in BCD. Registers E
through 1FFFF are user bytes and can be used to maintain data at the user’s discretion.
CLOCK ACCURACY (DIP MODULE)The DS1486 is guaranteed to keep time accuracy to within �1 minute per month at 25�C.
CLOCK ACCURACY (POWERCAP MODULE)The DS1486P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C.
DS1486/DS1486P
BLOCK DIAGRAM Figure 1
DS1486/DS1486P
TIME OF DAY REGISTERSRegisters 0, 1, 2, 4, 6, 8, 9, and A contain Time of Day data in BCD. Ten bits within these eight registers
are not used and will always read 0 regardless of how they are written. Bits 6 and 7 in the Months
Register (9) are binary bits. When set to logic 0, EOSC (Bit 7) enables the real-time clock oscillator. This
bit is set to logic 1 as shipped from Dallas Semiconductor to prevent lithium energy consumption during
storage and shipment (DIP Module only). This bit will normally be turned on by the user during device
initialization. However, the oscillator can be turned on and off as necessary by setting this bit to the
appropriate level. The INTA and Square Wave Output signals are tied together at pin 30 on the 32-pinDIP module. With this package, bit 6 of the Months Register (9) controls the function of this pin. When
set to logic 0, the pin will output a 1024 Hz square wave signal. When set to logic 1, the pin is available
for interrupt A output (INTA) only. The INTA and Square Wave Output signals are separated on the 34-
pin PowerCap module. With this package, bit 6 of the Months Register (9) controls only the Square Wave
Output (pin 33). When set to logic 0, pin 33 will output a 1024 Hz square wave signal. When set to logic
1, pin 33 is in a high impedance state. Pin 34 (INTA) is not affected by the setting of bit 6. Bit 6 of the
Hours register is defined as the 12- or 24-hour select bit. When set to logic 1, the 12-hour format isselected. In the 12-hour format, bit 5 is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5
is the second 10-hour bit (20-23 hours). The Time of Day registers are updated every 0.01 seconds from
the real-time clock, except when the TE bit (bit 7 of Register B) is set low or the clock oscillator is not
running. The preferred method of synchronizing data access to and from the RAMified Timekeeper is to
access the Command register by doing a write cycle to address location 0B and setting the TE bit(Transfer Enable bit) to a logic 0. This will freeze the External Time of Day registers at the present
recorded time, allowing access to occur without danger of simultaneous update. When the watch registers
have been read or written, a second write cycle to location 0B setting the TE bit to a logic 1 will put the
Time of Day Registers back to being updated every 0.01 second. No time is lost in the real-time clock
because the internal copy of the Time of Day register buffers is continually incremented while theexternal memory registers are frozen. An alternate method of reading and writing the Time of Day
registers is to ignore synchronization. However, any single reading may give erroneous data as the real-
time clock may be in the process of updating the external memory registers as data is being read. The
internal copies of seconds through years are incremented and the Time of Day Alarm is checked during
the period that hundreds of seconds reads 99. The copies are transferred to the external register whenhundredths of seconds roll from 99 to 00. A way of making sure data is valid is to do multiple reads and
compare. Writing the registers can also produce erroneous results for the same reasons. A way of making
sure that the write cycle has caused proper a update is to do read verifies and re-execute the write cycle if
data is not correct. While the possibility of erroneous results from read and write cycles has been stated, it
is worth noting that the probability of an incorrect result is kept to a minimum due to the redundantstructure of the RAMified Timekeeper.
TIME OF DAY ALARM REGISTERSRegisters 3, 5, and 7 contain the Time of Day Alarm Registers. Bits 3, 4, 5, and 6 of Register 7 will
always read 0 regardless of how they are written. Bit 7 of Registers 3, 5, and 7 are mask bits (Figure 3).
When all of the mask bits are logic 0, a Time of Day Alarm will only occur when Registers 2, 4, and 6match the values stored in Registers 3, 5, and 7. An alarm will be generated every day when bit 7 of
Register 7 is set to a logic 1. Similarly, an alarm is generated every hour when bit 7 of Registers 7 and 5
is set to a logic 1. When bit 7 of Registers 7, 5, and 3 is set to a logic 1, an alarm will occur every minute
when Register 1 (seconds) rolls from 59 to 00.
DS1486/DS1486P
WATCHDOG ALARM REGISTERSRegisters C and D contain the time for the Watchdog Alarm. The two registers contain a time count from
00.01to 99.99 seconds in BCD. The value written into the Watchdog Alarm Registers can be written or
read in any order. Any access to Register C or D will cause the Watchdog Alarm to reinitialize and clears
the Watchdog Flag bit and the Watchdog Interrupt Output. When a new value is entered or the Watchdog
Registers are read, the Watchdog Timer will start counting down from the entered value to 0. When 0 isreached, the Watchdog Interrupt Output will go to the active state. The Watchdog Timer Countdown is
interrupted and reinitialized back to the entered value every time either of the registers is accessed. In this
manner, controlled periodic accesses to the Watchdog Timer can prevent the Watchdog Alarm from
going to an active level. If access does not occur, countdown alarm will be repetitive. The Watchdog
Alarm Registers always read the entered value. The actual count-down register is internal and is notreadable. Writing registers C and D to 0 will disable the Watchdog Alarm feature.
DS1486 RAMIFIED TIMEKEEPER REGISTERS Figure 2
DS1486/DS1486P
TIME OF DAY ALARM MASK BITS Figure 3NOTE: ANY OTHER BIT COMBINATIONS OF MASK BIT SETTINGS PRODUCE ILLOGICAL OPERATION.
COMMAND REGISTERAddress location 0Bh is the Command Register where mask bits, control bits and flag bits reside. The
operation of each bit is as follows:
TE - Bit 7 Transfer enable - This bit when set to a logic 0 will disable the transfer of data between
internal and external clock registers. The contents in the external clock registers are now frozen and readsor writes will not be affected with updates. This bit must be set to a logic 1 to allow updates.
IPSW - Bit 6 Interrupt switch - When set to a logic 1, INTA is the Time of Day Alarm and INTB/(INTB)
is the Watchdog Alarm. When set to logic 0, this bit reverses the output pins. INTA is now the Watchdog
Alarm output and INTB/(INTB) is the Time of Day Alarm output. The INTA/SQW output pin shares both
the interrupt A and square wave output function. INTA and the square wave function should never be
simultaneously enabled or a conflict may occur (32-pin DIP module only).
IBH/LO - Bit 5 Interrupt B Sink or Source Current - When this bit is set to a logic 1 and VCC is applied,INTB/(INTB) will source current (see DC characteristics IOH). When this bit is set to a logic 0, INTBwill sink current (see DC characteristics IOL).
PU/LVL - Bit 4 Interrupt pulse mode or level mode - This bit determines whether both interrupts will
output a pulse or level signal. When set to a logic 0, INTA and INTB/(INTB) will be in the level mode.
When this bit is set to a logic 1, the pulse mode is selected and INTA will sink current for a minimum of
3 ms and then release. INTB/(INTB) will either sink or source current, depending on the condition of Bit
5, for a minimum of 3 ms and then release. INTB will only source current when there is a voltage present
on VCC.
WAM - Bit 3 Watchdog Alarm Mask - When this bit is set to a logic 0, the Watchdog Interrupt outputwill be activated. The activated state is determined by bits 1,4,5, and 6 of the COMMAND REGISTER.
When this bit is set to a logic 1, the Watchdog interrupt output is deactivated.
TDM - Bit 2 Time of Day Alarm Mask - When this bit is set to a logic 0, the Time of Day Alarm
Interrupt output will be activated. The activated state is determined by bits 0, 4, 5, and 6 of the
COMMAND REGISTER. When this bit is set to a logic 1, the Time of Day Alarm interrupt output is
deactivated.
WAF - Bit 1 Watchdog Alarm Flag - This bit is set to a logic 1 when a watchdog alarm interrupt occurs.This bit is read only.
DS1486/DS1486P
When the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only
during the time the interrupt is active.
TDF - Bit 0 Time of Day Flag - This is a read-only bit. This bit is set to a logic 1 when a Time of Dayalarm has occurred. The time the alarm occurred can be determined by reading the Time of Day Alarm
registers. This bit is reset to a logic 0 state when any of the Time of Day Alarm registers are accessed.
When the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only
during the time the interrupt is active.
DS1486/DS1486P
ABSOLUTE MAXIMUM RATINGS*Voltage on any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0�C to 70�C
Storage Temperature -40�C to + 70�C
Soldering Temperature 260�C for 10 seconds (See Note 14)This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0�C to 70�C)
DC ELECTRICAL CHARACTERISTICS (0�C to 70�C; VCC = 5V � 10%)
CAPACITANCE (tA = 25�C)
