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DS1481S+
1-Wire Bus Master with Overdrive
FEATURES Provides a synchronous interface to Dallas
Semiconductor 1-Wire devices Compatible with low power parallel ports
(can be used with microcontrollers) Can be cascaded with other DS1481s Allows print spooler and other processes to
run during 1-Wire I/O Provides high speed communication with
overdrive capable devices Space saving 14-pin (150 mil), SO package Recommended for short 1-Wire networks
less than 3 inches. Longer 1-Wire lengths
can be achieved with the DS2480B.
PIN CONFIGURATION
PIN DESCRIPTION VCC - Supply
ENI - Enable In
D/CLK - Data/Clock
RES - Reset
O1/BSY1 - Output 1/Busy 1
O2/BSY2 - Output 2/Busy 2
GND - Ground
I1 - Input 1
I2 - Input 2
I/O - 1-Wire
ENO - Enable Out
NC - No connection
DESCRIPTION The DS1481 is a dedicated 1-Wire® timing generator. The device is normally used in conjunction with a
parallel port controller to provide the necessary interface to the host processor. Busy signals allow the
host processor to perform other tasks while 1-Wire “time-slots” are completed. The DS1481 also saves
the state of D/CLK and RES, allowing print spoolers to operate without affecting 1-Wire communication.
DS1481 based devices can be cascaded. The first device’s O1/BSY1 and O2/BSY2 connect to the PC
printer port’s BUSY and SELECT OUT signals (pins 11 and 13 respectively). The next DS1481 connects
its O1/BSY1 and O2/BSY2 to the first device’s I1 and I2 respectively. ENO of the first device connects
to ENI of the second device. More DS1481s can be stacked in a similar manner. The last device’s I1 and
I2 connect to BUSY and SELECT of the attached printer.
DS1481
1-Wire Bus Master with Overdrive
Vcc 1 14 I/O
ENI 2 13 ENO
O1/BSY1 3 12 I1
O2/BSY2 4 11 I2
D/CLK 5 10 NC
RES 6 9 NC
NC 7 8 GND 14-PIN SO (150 MIL)
Not Recommended for New Design
DS1481
The DS1481’s 3V operation insures compatibility with most low power parallel ports (i.e., portable
computers).
DEVICE OPERATION 1-Wire communication is executed in “time slots”. The DS1481 generates either a read/write bit “time
slot” or a reset on the I/O pin. The operation performed is determined by the states of the D/CLK and
RES pins as follows:
TIME SLOT D/CLK RES Toggle Speed logic low logic low (see Figure 7)
Read 0, Read 1, Write 1 logic high logic high (see Figure 4)
Write 0 logic low logic high (see Figure 5)
1-Wire Reset logic high logic low (see Figure 6)
After D/CLK and RES have been set, the time slot begins when ENI is driven to its active state. A falling
edge on ENI causes the DS1481 to save the state of D/CLK and RES. If the time slot is a 1-Wire reset the
DS1481 will issue a busy signal by driving O1/BSY1 low and O2/BSY2 high. After 2μs O2/BSY2 is
driven low. Both outputs will remain low until the communication on the I/O line is finished. A busy
signal for a bit time slot differs from the reset busy signal only in that both O1/BSY1 and O2/BSY2 are
driven low immediately.
While the busy signal is asserted, the host processor is free to perform other tasks (including running the
print spooler). When the time slot is complete, the DS1481 restores both O1/BSY1 and O2/BSY2 to the
states of I1 and I2 (see Figure 1).
When the host detects that one or both of the busy signals has returned high, it must query the result of
the time slot. This is accomplished by driving D/CLK low. If the result of the time slot was low (Read 0,
Write 0 or presence detect) the DS1481 drives both O1/BSY1 and O2/BSY2 low (this state is held until
ENI returns high). Otherwise it propagates the states of I1 and I2.
After the host reads the result of the time slot it must drive ENI to its inactive state (high). The DS1481
will then set O1/BSY1 and O2/BSY2 to the states of I1 and
1-WIRE TIMING GENERATION For all time slots, the DS1481 samples the I/O pin at tSO (see Figure 4). The DS1481 waits a minimun of
60μs from the start of the time slot and de-asserts O1/BSY1 and O2/BSY2.
When a reset is requested, the DS1481 drives the I/O pin low for at least 480μs and then releases it.
During a normal reset the I/O pin immediately begins to return high.
If a 1-Wire device is present on the I/O line it pulls I/O low after time T (15μs ≤ T ≤ 60μs) from the
previous rising edge. The 1-Wire device(s) holds the I/O line low for 4T and then releases it, allowing the
I/O line to return high. This is the presence detect pulse. The I/O line must remain high (in its idle state)
for at least 3T before the 1-Wire device(s) is ready for further communication. To ensure this idle high
time is satisfied, the DS1481 does not release O1/BSY1 and O2/BSY2 for at least 960μs (measured from
the 1st falling edge on the I/O pin).
Not Recommended for New Design
DS1481
If after 480μs of low time the I/O line did not return high, either the I/O line has been shorted to ground
or there is at least one 1-Wire device connected to the I/O line which is issuing an alarm interrupt (see
Figure 6). In this case the DS1481 waits for I/O to return high for an additional 3840μs (64 * 60). If time
expires the I/O line is assumed to be shorted and the DS1481 releases O1/BSY1 and O2/BSY2. If the I/O
line returns high, the DS1481 continues to monitor the presence detect portion of the reset (as described
above) as for the non-interrupt case. Note that the 3T idle high time is still required after the presence
detect ends.
OVERDRIVE The DS1481 also supports overdrive communication with overdrive capable 1-Wire devices. When the
DS1481 powers up it is in normal mode (i.e., OD = 0, Figure 1). To toggle to overdrive mode the host
sets D/CLK and RES low and drives ENI low. The DS1481 toggles the OD bit to a logic high and returns
the states of I1 and I2 on O1/BSY1 and O2/BSY2. Overdrive mode is cleared in the same way. When
overdrive is turned off (OD = 0). O1/BSY1 and O2/BSY2 are driven low to report the state of the OD bit.
When OD = 1, communication with the 1-Wire device is exactly as described in the operation section
above. The actual 1-Wire timing for both modes of operation is described in Figures 4, 5, and 6.
Note that when toggling the OD bit there is no change on the I/O line.
PRINTER COEXISTENCE In order to coexist with parallel port printers, the DS1481 utilizes two input pins (I1 and I2) and two
output pins (O1/BSY1 and O2/BSY2). When ENI is low these pins are used for transmitting data
received on the I/O pin or for issuing an unmistakable busy signal. When ENI is inactive (high) O1/BSY1
and O2/BSY2 propagate the states of I1 and I2.
If a printer is attached to a DS1481, I1 is connected to the printers BUSY signal (low only if printer is on
line and busy), and I2 is connected to SELECT OUT (driven low if printer is off line), see Figure 2.
If the attached printer is “powered up” and on line, the DS1481 uses SELECT OUT for communication
regardless of the state of the printer’s BUSY signal. If the printer is off line its BUSY signal is inactive
(high) and this line is used by the DS1481 for host communication.
If the attached printer is powered off, both SELECT OUT and BUSY will be low. This prevents
meaningful communication with the DS1481 because it is unable to de-assert its busy signal (O1/BSY1
and O2/BSY2 low) or return a high sample of the I/O pin.
To solve this problem, the DS1481 uses the busy signal issued during a reset to detect the presence of
another DS1481 based device attached behind it on the parallel port. If this busy signal is not detected by
the DS1481, it assumes that it is the last DS1481 based device on the port.
If the DS1481 determines that it is the last device on the port it ignores the states of its I1 and I2 pins
while ENI is low. It also leaves the ENO pin high to prevent sending line feed signals to the printer. This
gives the last device the ability to control O1/BSY1 and O2/BSY2 without affecting stackability.
Not Recommended for New Design
DS1481
EPP/ECP TRANSPARENT MODE When the DS1481 first powers up it is in a transparent mode in which the three signal lines (auto line
feed, busy and select) that pass through the part are directly connected by transmission gates. This allows
bi-directional printers (or other parallel port peripherals) to communicate in either the EPP or ECP mode
of the PC parallel port. The DS1481 pin sets connected are as follows:
ENI ENO
O1/BSY1 I1
O2/BSY2 I2
1-Wire communication using the DS1481 is impossible in transparent mode. To toggle to normal mode
four consecutive overdrive toggle commands must be issued. If this sequence has been issued and the
ENI pin remains high for at least 10ms the part will enter its normal mode of operation. Note that any
other 1-Wire time slot command issued during the sequence resets the sequence. The steps needed to
return to transparent mode are as described above with the exception that no additional wait is required at
the end of the four overdrive toggles to enter transparent mode.
While in transparent mode if the DS1481 detects that the ENO pin has been held low for more than 10ms
it turns off the transmission gate connecting ENI and ENO. This guarantees the host will have the ability
to take the DS1481 out of transparent mode and perform 1-Wire I/O operations.
Figure 1. DS1481 FUNCTIONAL BLOCK DIAGRAM 50K
50K
50K50K
50K
50KO1/BSY1
O2/BSY2
I/O
RES
ENI
D/CLK
ENO
LAST PART
DETECTION
1-WIRE BUS
MASTER
D Q
CLK Q
D Q
CLK Q
Not Recommended for New Design
DS1481
Figure 2. CONNECTION TO PC TYPE PARALLEL PORTS
Figure 3. CONNECTION TO MICROCONTROLLERS The logic states of D/CLK and RES determine the type of 1-Wire function to be executed. These signals
are transferred into the DS1481 by activating ENI. This also activates the busy signals.
In Figures 4 through 6 below, during time slots or reset presence sequences the busy lines are active.
Once the busy state is over the computer queries the result of the time slot or reset presence sequence by
generating a falling edge on D/CLK. The result is found on the busy lines until ENI is de-activated.
TO PRINTER OR ANOTHER
PARALLEL PORT RESIDENT
DEVICE
TO HOST
+5
P14
P11
P13
P2
P3
P14
P11
P13
DS9100
P18
VCC
ENI
O1/BSY1
O2/BSY2
D/CLK
RES
NC
I/O
ENO
Auto Feed
Busy
Select
Data 1
Data 2
GND
+5
VCC
ENI
O1/BSY1
O2/BSY2
D/CLK
RES
NC
I/O
ENO
GND
DS9100
P1.0
P1.1
P1.2
P1.3
DS80C320
Not Recommended for New Design
DS1481
Figure 4. TIMING DIAGRAM: HOST INTERFACE
Figure 5. TIMING DIAGRAM: HOST INTERFACE tSIO = 8 μs (STANDARD SPEED), tBLB= 60 μs (MINIMUM)
tSIO = 2 μs (OVERDRIVE SPEED), tBLB= 6 μs (MINIMUM)
READ O, READ 1, WRITE 1 BIT TIME SLOTS
ENI
VALID
RESVALID
O1/BSY1
O2/BSY2
tBLB
READ 0
(I/O)
READ 1
(I/O)
WRITE 1
(I/O)
tSIO
ENI
D/CLK
VALID
RES
VALID
O1/BSY1
O2/BSY2
WRITE 0
(I/O)
tBLB = 60 μs (MINIMUM)
tBLB = 6 μs (MINIMUM)
(OD = 0)
(OD = 1)
WRITE 0 TIME SLOT
tBLB
D/CLK
(OD = 0)
(OD = 1)
Not Recommended for New Design
