DS1395 ,RAMified real time clockDS1395/DS1397DS1395/DS1397RAMified Real Time Clock
DS1397 ,RAMified real time clockPIN DESCRIPTIONS cessible. Registers are selected by the A0 line. Data isV V – Bus operational p ..
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DS1402-RP3+ ,1-Wire Network CablesFEATURES ORDERING INFORMATION DS1402D-DB8+ 2.4m (8ft) cable Coiled Cables Provide Flexible Connec ..
DS1413 ,Passive Serial Port iButton HolderFEATURES Small size, low-cost interface to an RS232C ®COM Port for reading and writing iButton de ..
DTC143TS , DTA/DTC SERIES
DTC143TS , DTA/DTC SERIES
DTC143XE , 100mA / 50V Digital transistors (with built-in resistors)
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DTC143XM , 100mA / 50V Digital transistors (with built-in resistors)
DTC143XS , DTA/DTC SERIES
DS1395-DS1397
RAMified real time clock
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to
Dallas Semiconductor databooks.
DS1395/DS1397RAMified Real Time Clock
DS1395/DS1397
BAT
SQWGND
V A0
SQW
BAT
V
SQW
BGND
STBY
IRQ
RESET
RTC
XRAM
IRQ
RESET
XRAM
RTC
STBY
IRQ
RESET
XRAM
RTC
DS1395S 28-Pin SOIC (330 mil)
DS1395 28-Pin DIP (600 mil)
DS1397 28-Pin Encapsulated Package (720 mil)
020794 1/19
FEATURESIdeal for EISA bus PCsFunctionally compatible with MC146818 in 32 KHz
modeTotally nonvolatile with over 10 years of operation in
the absence of powerSelf-contained subsystem includes lithium, quartz,
and support circuitryCounts seconds, minutes, hours, day of the week,
date, month, and year with leap year compensationBinary or BCD representations of time, calendar, and
alarm12- or 24-hour clock with AM and PM in 12-hour modeDaylight Savings Time optionInterfaced with software as 64 register/RAM locations
plus 4K x 8 of static RAM14 bytes of clock and control registers50 bytes of general and control registersSeparate 4K x 8 nonvolatile SRAMProgrammable square wave output signalBus-compatible interrupt signals (IRQ)Three interrupts are separately software-maskable
and testable:Time-of-day alarm once/second to once/dayPeriodic rates from 122 μs to 500 msEnd-of-clock update cycle28-pin JEDEC footprintAvailable as chip (DS1395/DS1395S) or stand alone
module with embedded lithium battery and crystal
(DS1397)
ORDERING INFORMATIONDS1395RTC Chip; 28–pin DIP
DS1395SRTC Chip; 28–pin SOIC
DS1397RTC Module; 28–pin DIP
PIN ASSIGNMENT
DS1395/DS1397
020794 2/19
PIN DESCRIPTIONS
VDD, VSS – Bus operational power is supplied to the partvia these pins. The voltage level present on these pins
should be monitored to transition between operational
power and battery power.
D0-D7 – Data Bus (bidirectional): Data is written intothe device from the data bus if either XRAM or RTC is
asserted during a write cycle at the rising edge of a WR
pulse. Data is read from the device and driven onto the
data bus if either XRAM or RTC is asserted during a
read cycle when the RD signal is low.
A0-A5 – Address Bus (input): Various internal regis-ters of the device are selected by these lines. When
RTC is asserted, A0 selects between the indirect ad-
dress register and RTC data register. When the XRAM
is asserted, A0-A5 addresses a 32–byte page of RAM.
When A5 is high, the RAM page register is accessible.
When A5 is low, A0-A4 address the 32-byte page of
RAM.
RD - Read Strobe (input): Data is read from the se-lected register and driven onto the data bus by the de-
vice when this line is low and either RTC or XRAM is as-
serted.
WR - Write Strobe (input): Data is written into the de-vice from the data bus on the rising edge after a low
pulse on this line when the device has been selected by
either the XRAM or RTC signals.
STBY - Standby (input): Accesses to the device areinhibited and outputs are tri-stated to a high impedance
state when this signal is asserted low. All data in RAM of
the device is preserved. The real time clock continues
to keep time.
If a read or write cycle is in progress when the STBY sig-
nal is asserted low, the internal cycle will be terminated
when either the external cycle completes or when the in-
ternal chip enable condition (VDD is 4.25 volts, typical) is
negated, whichever occurs first.
RTC - Real Time Clock Select (input): When this sig-nal is asserted low, the real time clock registers are ac-
cessible. Registers are selected by the A0 line. Data is
driven onto the data bus when RD is low. Data is re-
ceived from the bus when WR is pulsed low and then
high.
SQW - Square Wave (output): Frequency selectableoutput. Frequency is selected by setting register A bits
RS0-RS3. See Table 2 for frequencies that can be se-
lected.
XRAM - Extended RAM Select (input): When this sig-nal is asserted low, the extended RAM bytes are acces-
sible. The XRAM page register is selected when the A5
address line is high. A 32-byte page of RAM is accessi-
ble when A5 is low. A0-A4 select the bytes within the
page of RAM pointed to by the page register. Data is
driven onto the data bus when RD is low. Data is re-
ceived from the bus when WR is pulsed low and then
high.
IRQ - Interrupt Request (output): The IRQ signal is anactive low, open drain output that is used as a processor
interrupt request. The IRQ output follows the state of
the IRQF bit (bit 7) in status register C. IRQ can be as-
serted by the alarm, update ended, or periodic interrupt
functions depending on the configuration of register B.
RESET - Reset (input): The reset signal is used to ini-tialize certain registers to allow proper operation of the
RTC module. When RESET is low, the following oc-
curs.The following register bits are cleared:Periodic interrupt (PIE)Alarm interrupt enable (AIE)Update ended interrupt (UF)Interrupt request flag (IRQF)Periodic interrupt flag (PF)Alarm interrupt flag (AF)Square wave output enable (SQWE)Update ended interrupt enable (UIE)The IRQ pin is in the high impedance state.The RTC is not processor accessible.
DS1395/DS1397
020794 3/19
ADDITIONAL PIN DESCRIPTION
(FOR DS1395, DS1395S)
X1, X2 – Connections for a standard 32.768 KHz quartzcrystal, Daiwa part number DT-26S or equivalent. The
internal oscillator circuitry is designed for operation with
a crystal having a specified load capacitance (CL) of
6 pF. The crystal is connected directly to the X1 and X2
pins. There is no need for external capacitors or resis-
tors. Note: X1 and X2 are very high impedance nodes.
It is recommended that they and the crystal be guard–
ringed with ground and that high frequency signals be
kept away from the crystal area. For more information
on crystal selection and crystal layout considerations,
please consult Application Note 58, “Crystal Consider-
ations with Dallas Real Time Clocks”.
VBAT – Battery input for any standard +3 volt lithium cellor other energy source. Battery voltage must be held
between 2.5 and 3.5 volts for proper operation. The
nominal write protect trip point voltage at which access
to the real time clock and user RAM is denied is set by
the internal circuitry as 1.26 x VBAT. A maximum load of
1 μA at 25oC and 3.0V on VBAT in the absence of power
should be used to size the external energy source.
The battery should be connected directly to the VBAT
pin. A diode must not be placed in series with the battery
to the VBAT pin. Furthermore, a diode is not necessary
because reverse charging current protection circuitry is
provided internal to the device and has passed the
requirements of Underwriters Laboratories for UL list-
ing.
BGND – Battery ground: This pin or pin 14 can be usedfor the battery ground return.
OPERATION
Power-Down/Power-Up: The real time clock will con-tinue to operate and all of the RAM, time, and calendar
and alarm memory locations will remain non-volatile re-
gardless of the voltage level of VDD. When the voltage
level applied to the VDD input is greater than 4.25 volts
(typical), the module becomes accessible after 200 ms
provided that the oscillator and countdown chain have
been programmed to be running. This time period al-
lows the module to stabilize after power is applied.
When VDD falls below the CETHR (4.25 volts typical), the
chip select inputs RTC and XRAM are forced to an inac-
tive state regardless of the state of the pin signals. This
puts the module into a write protected mode in which all
inputs are ignored and all outputs are in a high imped-
ance state. When VDD falls below 3.2 volts (typical), the
module is switched over to an internal power source in
the case of the DS1397, or to an external battery con-
nected to the VBAT and BGND pins in the case of the
DS1395 and DS1395S, so that power is not interrupted
to timekeeping and nonvolatile RAM functions.
Address Map: The registers of the device appear in twodistinct address ranges. One set of registers is active
when RTC is asserted low and represents the real time
clock. The second set of registers is active when XRAM
is asserted low and represents the extended RAM.
RTC Address Map: The address map of the RTC mod-ule is shown in Figure 2. The address map consists of
50 bytes of general purpose RAM, 10 bytes of RTC/cal-
endar information, and 4 bytes of status and control in-
formation. All 64 bytes can be accessed as read/write
registers except for the following:Registers C and D are Read Only (status informa-
tion)Bit 7 of register A is Read OnlyBit 7 of the ”Seconds” byte (00) is Read Only
The first byte of the real time clock address map is the
RTC indirect address register, accessible when A0 is
low. The second byte is the RTC data register, accessi-
ble when A0 is high. The function of the RTC indirect ad-
dress register is to point to one of the 64 RTC registers
that are indirectly accessible through the RTC data reg-
ister.
Extended RAM Address Map: The first 32 bytes of theextended RAM represent one of 128 pages of general
purpose nonvolatile memory. These 32 bytes on a page
are addressed by A0 through A4 when A5 is low. When
A5 is high, the XRAM page register is accessible. The
value in the XRAM page register points to one of 128
pages of nonvolatile memory available. The address of
the XRAM page register is dependent only on A5 being
high; thus, there are 31 aliases of this register in I/0
spaces. (See Figure 3.)
DS1395/DS1397
020794 4/19
TIME, CALENDAR AND ALARM LOCATIONSThe time and calendar information is obtained by read-
ing the appropriate register bytes shown in Table 1. The
time, calendar, and alarm are set or initialized by writing
the appropriate register bytes. The contents of the time,
calendar, and alarm registers can be either Binary or
Binary-Coded Decimal (BCD) format. Table 1 shows
the binary and BCD formats of the twelve time, calendar,
and alarm locations.
Before writing the internal time, calendar, and alarm reg-
isters, the SET bit in Register B should be written to a
logic one to prevent updates from occurring while ac-
cess is being attempted. Also at this time, the data for-
mat (binary or BCD), should be set via the data mode bit
(DM) of Register B. All time, calendar, and alarm regis-
ters must use the same data mode. The set bit in Regis-
ter B should be cleared after the data mode bit has been
written to allow the real-time clock to update the time
and calendar bytes.
Once initialized, the real-time clock makes all updates in
the selected mode. The data mode cannot be changed
without reinitializing the ten data bytes. The 24/12 bit
cannot be changed without reinitializing the hour loca-
tions. When the 12-hour format is selected, the high or-
der bit of the hours byte represents PM when it is a logic
one. The time, calendar, and alarm bytes are always ac-
cessible because they are double buffered. Once per
second the ten bytes are advanced by one second and
checked for an alarm condition. If a read of the time and
calendar data occurs during an update, a problem exists
where seconds, minutes, hours, etc. may not correlate.
The probability of reading incorrect time and calendar
data is low. Several methods of avoiding any possible
incorrect time and calendar reads are covered later in
this text.
The three alarm bytes can be used in two ways. First,
when the alarm time is written in the appropriate hours,
minutes, and seconds alarm locations, the alarm inter-
rupt is initiated at the specified time each day if the alarm
enable bit is high . The second method is to insert a
“don’t care” state in one or more of the three alarm bytes.
The “don’t care” code is any hexadecimal value from C0
to FF. The two most significant bits of each byte set the
“don’t care” condition when at logic 1. An alarm will be
generated each hour when the “don’t care” bits are set in
the hours byte. Similarly, an alarm is generated every
minute with “don’t care” codes in the hours and minute
alarm bytes. The “don’t care” codes in all three alarm
bytes create an interrupt every second.
DS1395/DS1397
020794 5/19
DS139X BLOCK DIAGRAM Figure 1SQW
RST
IRQ
STBYRT
XRAM
XRAM
THRU
XRAM + 1F
XRAM + 20
XRAM + 21
THRU
XRAM + 3F
PAGE 7F
DS1395/DS1397
020794 6/19
REAL TIME CLOCK RAM MAP Figure 2RTC
RTC +1
INDIRECT
ADDRESS
00
EXTENDED RAM ADDRESS MAP Figure 3
DS1395/DS1397
020794 7/19
TIME, CALENDAR AND ALARM DATA MODES Table 1
USER NONVOLATILE RAM - RTCThe 50 user nonvolatile RAM bytes are not dedicated to
any special function within the DS1395/DS1397. They
can be used by the application program as nonvolatile
memory and are fully available during the update cycle.
This memory is directly accessible in the RTC section.
INTERRUPTSThe RTC plus RAM includes three separate, fully auto-
matic sources of interrupt for a processor. The alarm in-
terrupt can be programmed to occur at rates from once
per second to once per day. The periodic interrupt can
be selected for rates from 500 ms to 122 μs. The up-
date-ended interrupt can be used to indicate to the pro-
gram that an update cycle is complete. Each of these
independent interrupt conditions is described in greater
detail in other sections of this text.
The application program can select which interrupts, if
any, are going to be used. Three bits in Register B en-
able the interrupts. Writing a logic 1 to an interrupt-en-
able bit permits that interrupt to be initiated when the
event occurs. A logic 0 in an interrupt-enable bit prohib-
its the IRQ pin from being asserted from that interrupt
condition. If an interrupt flag is already set when an in-
terrupt is enabled, IRQ is immediately set at an active
level, although the interrupt initiating the event may
have occurred much earlier. As a result, there are cases
where the program should clear such earlier initiated in-
terrupts before first enabling new interrupts.
When an interrupt event occurs, the relating flag bit is
set to logic 1 in Register C. These flag bits are set inde-
pendent of the state of the corresponding enable bit in
Register B. The flag bit can be used in a polling mode
without enabling the corresponding enable bits. When a
flag is set, an indication is given to software that an inter-
rupt event has occurred since the flag bit was last read.
However, care should be taken when using the flag bits
as they are cleared each time Register C is read.
Double latching is included with Register C so that bits
which are set remain stable throughout the read cycle.
All bits which are set (high) are cleared when read and
new interrupts which are pending during the read cycle
are held until after the cycle is completed. One, two, or
three bits can be set when reading Register C. Each uti-
lized flag bit should be examined when read to ensure
that no interrupts are lost.
The alternative flag bit usage method is with fully en-
abled interrupts. When an interrupt flag bit is set and the
corresponding interrupt enable bit is also set, the IRQ
pin is asserted low. IRQ is asserted as long as at least
one of the three interrupt sources has its flag and enable
bits both set. The IRQF bit in Register C is a one when-
ever the IRQ pin is being driven low. Determination that
DS1395/DS1397
020794 8/19
the RTC initiated an interrupt is accomplished by read-
ing Register C. A logic one in bit 7 (IRQF bit) indicates
that one or more interrupts have been initiated by the
DS1395/DS1397. The act of reading Register C clears
all active flag bits and the IRQF bit.
OSCILLATOR CONTROL BITSWhen the DS1395/DS1397 is shipped from the factory,
the internal oscillator is turned off. This feature prevents
the lithium battery from being used until it is installed in a
system. A pattern of 010 in bits 4 through 6 of Register A
will turn the oscillator on and enable the countdown
chain. A pattern of 11X will turn the oscillator on, but
holds the countdown chain of the oscillator in reset. All
other combinations of bits 4 through 6 keep the oscilla-
tor off.
SQUARE WAVE OUTPUT SELECTIONThirteen of the 15 divider taps are made available to a
1-of-15 selector, as shown in the block diagram of Fig-
ure 1. The first purpose of selecting a divider tap is to
generate a square wave output signal on the SQW pin.
The RS0-RS3 bits in Register A establish the square
wave output frequency. These frequencies are listed in
Table 2. The SQW frequency selection shares its
1-of-15 selector with the periodic interrupt generator.
Once the frequency is selected, the output of the SQW
pin can be turned on and off under program control with
the square wave enable bit (SQWE).
PERIODIC INTERRUPT SELECTIONThe periodic interrupt will cause the IRQ pin to go to an
active state from once every 500 ms to once every
122 μs. This function is separate from the alarm inter-
rupt which can be output from once per second to once
per day. The periodic interrupt rate is selected using the
same Register A bits which select the square wave fre-
quency (see Table 1). Changing the Register A bits af-
fects both the square wave frequency and the periodic
interrupt output. However, each function has a separate
enable bit in Register B. The SQWE bit controls the
square wave output. Similarly, the periodic interrupt is
enabled by the PIE bit in Register B. The periodic inter-
rupt can be used with software counters to measure in-
puts, create output intervals, or await the next needed
software function.
PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 2
DS1395/DS1397
020794 9/19
UPDATE CYCLEThe DS1395/DS1397 executes an update cycle once
per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to one, the user
copy of the double buffered time, calendar, and alarm
bytes is frozen and will not update as the time incre-
ments. However, the time countdown chain continues
to update the internal copy of the buffer. This feature al-
lows time to maintain accuracy independent of reading
or writing the time, calendar, and alarm buffers and also
guarantees that time and calendar information is con-
sistent. The update cycle also compares each alarm
byte with the corresponding time byte and issues an
alarm if a match or if a “don’t care” code is present in all
three positions.
There are three methods that can handle access of the
real-time clock that avoid any possibility of accessing in-
consistent time and calendar data. The first method
uses the update-ended interrupt. If enabled, an inter-
rupt occurs after every update cycle that indicates that
over 999 ms are available to read valid time and date in-
formation. If this interrupt is used, the IRQF bit in Regis-
ter C should be cleared before leaving the interrupt rou-
tine.
A second method uses the update-in-progress bit (UIP)
in Register A to determine if the update cycle is in prog-
ress. The UIP bit will pulse once per second. After the
UIP bit goes high, the update transfer occurs 244 μs lat-
er. If a low is read on the UIP bit, the user has at least
244 μs before the time/calendar data will be changed.
Therefore, the user should avoid interrupt service rou-
tines that would cause the time needed to read valid
time/calendar data to exceed 244 μs.
The third method uses a periodic interrupt to determine
if an update cycle is in progress. The UIP bit in Register
A is set high between the setting of the PF bit in Register
C (see Figure 3). Periodic interrupts that occur at a rate
of greater than tBUC allow valid time and date informa-
tion to be reached at each occurrence of the periodic in-
terrupt. The reads should be complete within
(tPI/2+tBUC) to ensure that data is not read during the up-
date cycle.
UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 4UIP BIT IN
REGISTER A
UF BIT IN
REGISTER C
PF BIT IN
REGISTER CPI
PI/2
tPI = Periodic interrupt time interval per Table 1.
tBUC = Delay time before update cycle = 244 μs.
DS1395/DS1397
020794 10/19
REGISTERSThe DS1395/DS1397 has four control registers which
are accessible at all times, even during the update
cycle.
REGISTER A
MSB LSB
UIP - The Update In Progress (UIP) bit is a status flagthat can be monitored. When the UIP bit is a one, the
update transfer will soon occur. When UIP is a zero, the
update transfer will not occur for at least 244 μs. The
time, calendar, and alarm information in RAM is fully
available for access when the UIP bit is zero. The UIP
bit is read only. Writing the SET bit in Register B to a one
inhibits any update transfer and clears the UIP status
bit.
DV2, DV1, DV0 - These three bits are used to turn theoscillator on or off and to reset the countdown chain. A
pattern of 010 is the only combination of bits that will turn
the oscillator on and allow the RTC to keep time. A pat-
tern of 11X will enable the oscillator but holds the count-
down chain in reset. The next update will occur at 500
ms after a pattern of 010 is written to DV2, DV1, and
DV0.
RS3, RS2, RS1, RS0 - These four rate-selection bits se-lect one of the 13 taps on the 15-stage divider or disable
the divider output. The tap selected can be used to gen-
erate an output square wave (SQW pin) and/or a period-
ic interrupt. The user can do one of the followingEnable the interrupt with the PIE bit;Enable the SQW output pin with the SQWE bit;Enable both at the same time and the same rate; orEnable neither.
Table 2 lists the periodic interrupt rates and the square
wave frequencies that can be chosen with the RS bits.
REGISTER B
MSB LSB
SET - When the SET bit is a zero, the update transferfunctions normally by advancing the counts once per
second. When the SET bit is written to a one, any update
transfer is inhibited and the program can initialize the
time and calendar bytes without an update occurring in
the midst of initializing. Read cycles can be executed in
a similar manner. SET is a read/write bit that is not modi-
fied by internal functions of the DS1395/DS1397.
PIE - The Periodic Interrupt Enable bit is a read/write bitwhich allows the Periodic Interrupt Flag (PF) bit in Reg-
ister C to drive the IRQ pin low. When the PIE bit is set to
one, periodic interrupts are generated by driving the
IRQ pin low at a rate specified by the RS3-RS0 bits of
Register A. A zero in the PIE bit blocks the IRQ output
from being driven by a periodic interrupt, but the Period-
ic Flag (PF) bit is still set at the periodic rate. PIE is not
modified by any internal DS1395/DS1397 functions but
is cleared by the hardware RESET signal.
AIE - The Alarm Interrupt Enable (AIE) bit is a read/writebit which, when set to a one, permits the Alarm Flag (AF)
bit in register C to assert IRQ. An alarm interrupt occurs
for each second that the three time bytes equal the three
alarm bytes including a don’t care alarm code of binary
11XXXXXX. When the AIE bit is set to zero, the AF bit
does not initiate the IRQ signal. The internal functions of
the DS1395/DS1397 do not affect the AIE bit but is
cleared by RESET.
UIE - The Update Ended Interrupt Enable (UIE) bit is aread/write bit that enables the Update Ended Flag (UF)
bit in Register C to assert IRQ. The SET bit going high or
the RESET pin going low clears the UIE bit.
SQWE - When the Square Wave Enable (SQWE) bit isset to a one, a square wave signal at the frequency set
by the rate-selection bits RS3 through RS0 is driven out
on a SQW pin. When the SQWE bit is set to zero, the
SQW pin is held low. SQWE is a read/write bit and is
cleared by RESET.
DM - The Data Mode (DM) bit indicates whether timeand calendar information is in binary or BCD format.
The DM bit is set by the program to the appropriate for-
mat and can be read as required. This bit is not modified
by internal functions. A one in DM signifies binary data
while a zero in DM specifies Binary Coded Decimal
(BCD) data.
