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DS1345YP-100+
1024k Nonvolatile SRAM with Battery Monitor
FEATURES 10 years minimum data retention in the
absence of external power Data is automatically protected during power
loss Power supply monitor resets processor when
VCC power loss occurs and holds processor in
reset during VCC ramp-up Battery monitor checks remaining capacity
daily Read and write access times of 70ns Unlimited write cycle endurance Typical standby current 50µA Upgrade for 128k x 8 SRAM, EEPROM or
Flash Lithium battery is electrically disconnected to
retain freshness until power is applied for the
first time Full ±10% VCC operating range (DS1345Y)
or optional ±5% VCC operating range
(DS1345AB) Optional industrial temperature range of
-40°C to +85°C, designated IND PowerCap Module (PCM) package Directly surface-mountable module Replaceable snap-on PowerCap provides
lithium backup battery Standardized pinout for all nonvolatile
(NV) SRAM products Detachment feature on PowerCap allows
easy removal using a regular screwdriver
PIN ASSIGNMENT
PIN DESCRIPTION A0 – A16 - Address Inputs
DQ0 – DQ7 - Data In/Data Out - Chip Enable - Write Enable - Output Enable
RST - Reset Output - Battery Warning Output
VCC - Power (+5V)
GND - Ground
NC - No Connect
DESCRIPTION The DS1345 1024k NV SRAMs are 1,048,576-bit, fully static, NV SRAMs organized as 131,072 words
by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which
constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium
energy source is automatically switched on and write protection is unconditionally enabled to prevent
data corruption. Additionally, the DS1345 devices have dedicated circuitry for monitoring the status of
VCC and the status of the internal lithium battery. DS1345 devices in the PowerCap module package are
DS1345Y/AB
1024k Nonvolatile SRAM
with Battery Monitor
BW 2 3 A15
A16 RST VCC
WE
OE
CE DQ7
DQ6
DQ5 DQ4
DQ3
DQ2 DQ1
DQ0
GND 6 8 9
10 11
12 13
14 15
16 17
NC A14
33
32 31
30
29 28 27 26
25 24 23
22
21
20 19
18
A13
A12 A11
A10 A9 A8
A7 A6
A5 A4
A3 A2
A1
A0
34 NC
GND VBAT
34-Pin PowerCap Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
19-5589; Rev 10/10
DS1345Y/AB
READ MODE The DS1345 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 17 address inputs
(A0 – A16) defines which of the 131,072 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE The DS1345 devices execute a write cycle whenever the WE and CE signals are in the active (low) state
after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of
the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE The DS1345AB provides full functional capability for VCC greater than 4.75V and write protects by 4.5V.
The DS1345Y provides full functional capability for VCC greater than 4.5V and write protects by 4.25V.
Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static
RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write
protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls
below approximately 2.7V, the power switching circuit connects the lithium energy source to RAM to
retain data. During power-up, when VCC rises above approximately 2.7V, the power switching circuit
connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation
can resume after VCC exceeds 4.75V for the DS1345AB and 4.5V for the DS1345Y.
SYSTEM POWER MONITORING DS1345 devices have the ability to monitor the external VCC power supply. When an out-of-tolerance
power supply condition is detected, the NV SRAMs warn a processor-based system of impending power
failure by asserting RST. On power-up, RST is held active for 200ms nominal to prevent system
operation during power-on transients and to allow tREC to elapse. RST has an open drain output driver.
BATTERY MONITORING The DS1345 devices automatically perform periodic battery voltage monitoring on a 24-hour time
interval. Such monitoring begins within tREC after VCC rises above VTP and is suspended when power
failure occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1MΩ test resistor for one
second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output BW is asserted. Once asserted, BW remains active until the module is replaced.
The battery is still retested after each VCC power-up, however, even if BW is active. If the battery voltage
is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing
DS1345Y/AB
PACKAGES The 34-pin PowerCap Module integrates SRAM memory and NV control along with contacts for
connection to the lithium battery in the DS9034PC PowerCap. The PowerCap module package design
allows a DS1345 PCM device to be surface mounted without subjecting its lithium backup battery to
destructive high-temperature reflow soldering. After a DS1345 PCM is reflow soldered, a DS9034PC is
snapped on top of the PCM to form a complete NV SRAM module. The DS9034PC is keyed to prevent
improper attachment. DS1345 PowerCap modules and DS9034PC PowerCaps are ordered separately and
shipped in separate containers. See the DS9034PC data sheet for further information.
DS1345Y/AB
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Storage Temperature Range -55°C to +125°C
Lead Temperature (soldering, 10s) +260°C
Soldering Temperature (reflow) +260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1345AB Power Supply Voltage VCC 4.75 5.0 5.25 V
DS1345Y Power Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 0.8 V
DC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 5% for DS1345AB)
(TA: See Note 10) (VCC = 5V ± 10% for DS1345Y)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current IIL -1.0 +1.0 µA
I/O Leakage Current CE ≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current @ 2.4V IOH -1.0 mA 14
Output Current @ 0.4V IOL 2.0 mA 14
Standby Current CE= 2.2V ICCS1 200 600 µA
Standby Current CE= VCC-0.5V ICCS2 50 150 µA
Operating Current ICCO1 85 mA
Write Protection Voltage (DS1345AB) VTP 4.50 4.62 4.75 V
Write Protection Voltage (DS1345Y) VTP 4.25 4.37 4.5 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 5 10 pF
Input/Output Capacitance CI/O 5 10 pF
DS1345Y/AB
AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 5% for DS1345AB)
(TA: See Note 10) (VCC = 5V ± 10% for DS1345Y)
PARAMETER SYMBOL
DS1345AB-70
DS1345Y-70 UNITS NOTES
MIN MAX
Read Cycle Time tRC 70 ns
Access Time tACC 70 ns to Output Valid tOE 35 ns to Output Valid tCO 70 ns or CE to Output Active tCOE 5 ns 5
Output High Z from Deselection tOD 25 ns 5
Output Hold from Address
Change tOH 5 ns
Write Cycle Time tWC 70 ns
Write Pulse Width tWP 55 ns 3
Address Setup Time tAW 0 ns
Write Recovery Time tWR1
tWR2
12 ns 12
13
Output High Z from WE tODW 25 ns 5
Output Active from WE tOEW 5 ns 5
Data Setup Time tDS 30 ns 4
Data Hold Time tDH1
tDH2 ns 12
13
READ CYCLE
SEE NOTE 1
DS1345Y/AB
WRITE CYCLE 1 SEE NOTES 2, 3, 4, 6, 7, 8, and 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
