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DS1340C-33#-DS1340U-33+T&R-DS1340Z-33+T&R
I²C RTC with Trickle Charger
DS1340I2C RTC with Trickle Charger
General DescriptionThe DS1340 is a real-time clock (RTC)/calendar that is
pin compatible and functionally equivalent to the ST
M41T00, including the software clock calibration. The
device additionally provides trickle-charge capability
on the VBACKUPpin, a lower timekeeping voltage, and
an oscillator STOP flag. Block access of the register
map is identical to the ST device. Two additional regis-
ters, which are accessed individually, are required for
the trickle charger and flag. The clock/calendar pro-
vides seconds, minutes, hours, day, date, month, and
year information. A built-in power-sense circuit detects
power failures and automatically switches to the back-
up supply. Reads and writes are inhibited while the
clock continues to run. The device is programmed seri-
ally through an I2C bidirectional bus.
ApplicationsPortable Instruments
Point-of-Sale Equipment
Medical Equipment
Telecommunications
Benefits and FeaturesEnhanced Second Source for the ST M41T00
Completely Manages All Timekeeping FunctionsRTC Counts Seconds, Minutes, Hours, Day, Date,
Month, and YearSoftware Clock CalibrationOscillator Stop Flag
Low-Power Operation Extends Battery Backup Run
TimeLow Timekeeping Voltage Down to 1.3VAutomatic Power-Fail Detect and Switch CircuitryTrickle-Charge Capability
Three Operating Voltage Ranges (1.8V, 3V, and 3.3V)
Supports Systems Using Legacy and Modern Power
Buses
Surface-Mount Package with an Integrated Crystal
(DS1340C) Saves Additional Spaceand Simplifies
Design
Simple Serial Port Interfaces withMost MicrocontrollersFast (400kHz) I2CInterface
8-Pin µSOP or SO Package Minimizes Required
Space
Underwriters Laboratories (UL®) Recognized
Ordering Information
CPUVCC
VCC
VCC12
SDA
SCL
GNDX1
VCCRPURPU
CRYSTAL
FT/OUT
VBACKUP3
RPU = tR / CB
DS1340
Typical Operating Circuit
PARTTEMP RANGEPIN-
PACKAGETOP MARK†DS1340Z-18+ -40°C to +85°C 8 SO
(0.150in) D1340-18
DS1340Z-3+ -40°C to +85°C 8 SO
(0.150in) DS1340-3
DS1340Z-33+ -40°C to +85°C 8 SO
(0.150in) D134033
DS1340U-18+ -40°C to +85°C 8 μSOP 1340 -18
DS1340U-3+ -40°C to +85°C 8 μSOP 1340 -3
DS1340U-33+ -40°C to +85°C 8 μSOP 1340 -33
DS1340C-18# -40°C to +85°C 16 SO DS1340C-18
DS1340C-3# -40°C to +85°C 16 SO DS1340C-3
DS1340C-33# -40°C to +85°C 16 SO DS1340C-33
Pin Configurations appear at end of data sheet.+Denotes a lead(Pb)-free/RoHS-compliant package.
#Denotes a RoHS-compliant device that may include lead(Pb)
that is exempt under RoHS requirements. The lead finish is
JESD97 category e3, and is compatible with both lead-based
and lead-free soldering processes.
†A "+" anywhere on the top mark denotes a lead(Pb)-free device.
A "#" denotes a RoHS-compliant device.UL is a registered trademark of Underwriters Laboratories Inc.
DS1340I2C RTC with Trickle Charger
Absolute Maximum Ratings
Recommended DC Operating Conditions(VCC= VCC MINto VCC MAX, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= 3.3V, TA= +25°C, unless
otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCCor VBACKUPPins
Relative to Ground.............................................-0.3V to +6.0V
Voltage Range on SDA, SCL, and FT/OUT
Relative to Ground..................................-0.3V to (VCC+ 0.3V)
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +125°C
Lead Temperature (soldering, 10s).................................+260°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDS1340-18 1.71 1.8 5.5
DS1340-3 2.7 3.0 5.5 Supply Voltage (Note 2) VCC
DS1340-33 2.97 3.3 5.5
Input Logic 1 (SDA, SCL) VIH (Note 2) 0.7 x VCC VCC + 0.3 V
Input Logic 0 (SDA, SCL) VIL (Note 2) -0.3 +0.3 x VCC V
Supply Voltage, Pullup
(FT/OUT, SDA, SCL), VCC = 0V VPU (Note 2) 5.5 V
DS1340-18 1.3 3.7
DS1340-3 1.3 3.7 Backup Supply Voltage (Note 2) VBACKUP
DS1340-33 1.3 5.5
R1 (Notes 3, 4) 250
R2 (Note 5) 2000 Trickle-Charge Current-Limiting
Resistors
R3 (Note 6) 4000
DS1340-18 1.51 1.6 1.71
DS1340-3 2.45 2.6 2.7 Power-Fail Voltage (Note 2) VPF
DS1340-33 2.70 2.88 2.97
Input Leakage (SCL, CLK) ILI -1 +1 μA
I/O Leakage (SDA, FT/OUT) ILO -1 +1 μA
VCC > 2V; VOL = 0.4V 3.0 SDA Logic 0 Output IOLSDA1.7V < VCC < 2V; VOL = 0.2 x VCC 3.0 mA
VCC > 2V; VOL = 0.4V 3.0
1.7V < VCC < 2V; VOL = 0.2 x VCC 3.0 mA FT/OUT Logic 0 Output IOLSQW
1.3V < VCC < 1.7V; VOL = 0.2x VCC 250 μA
DS1340-18; VCC = 1.89V 72 150
DS1340-3; VCC = 3.3V 108 200 Active Supply Current (Note 7) ICCA
DS1340-33; VCC = 5.5V 192 300
μA
DS1340-18; VCC = 1.89V 60 100
DS1340-3; VCC = 3.3V 81 125 Standby Current (Note 8) ICCS
DS1340-33; VCC = 5.5V 100 150
μA
VBACKUP Leakage Current IBACKUPLKG VBACKUP = 3.7V 100 nA
DS1340I2C RTC with Trickle Charger
DC Electrical Characteristics(VCC= 0V, VBACKUP= 3.7V, TA= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS IBACKUP1 OSC ON, FT = 0 (Note 9) 800 1150
IBACKUP2 OSC ON, FT = 1 (Note 9) 850 1250 VBACKUP Current
IBACKUP3OSC ON, FT = 0, VBACKUP = 3.0V,
TA = +25°C (Notes 9, 10) 800 1000
nA
VBACKUP Data-Retention Current IBACKUPDR OSC OFF 25.0 100 nA
AC Electrical Characteristics(VCC= VCCMINto VCCMAX, TA= -40°C to +85°C, unless otherwise noted.) (Notes 1,14, Figure 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSStandard mode 0 100 SCL Clock Frequency fSCLFast mode 100 400 kHz
Standard mode 4.7 Bus Free Time Between STOP
and START Conditions tBUFFast mode 1.3 μs
Standard mode 4.0 Hold Time (Repeated) START
Condition (Note 11) tHD:STAFast mode 0.6 μs
Standard mode 4.7 Low Period of SCL Clock tLOW
Fast mode 1.3
μs
Standard mode 4.0 High Period of SCL Clock tHIGHFast mode 0.6 μs
Standard mode 0 0.9 Data Hold Time (Notes 12, 13) tHD:DATFast mode 0 0.9 μs
Standard mode 250 Data Setup Time (Note 14) tSU:DATFast mode 100 ns
Standard mode 4.7 START Setup Time tSU:STA
Fast mode 0.6
μs
Standard mode 20 + 0.1CB 1000 Rise Time of SDA and SCL
Signals (Note 15) tRFast mode 20 + 0.1CB 300 ns
Standard mode 20 + 0.1CB 300 Fall Time of SDA and SCL
Signals (Note 15) tFFast mode 20 + 0.1CB 300 ns
Standard mode 4.7 Setup Time for STOP Condition tSU:STOFast mode 0.6 μs
Capacitive Load for Each Bus
Line CB (Note 15) 400 pF
I/O Capacitance (SCL, SDA) CI/O 10 pF
Pulse Width of Spikes that Must
be Suppressed by the Input
Filter
tSP Fast mode 30 ns
Oscillator Stop Flag (OSF) Delay tOSF (Note 16) 100 ms
DS1340I2C RTC with Trickle Charger
Power-Up/Power-Down Characteristics(TA= -40°C to +85°C) (Figure 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSRecovery at Power-UptREC(Note 17)2ms
VCC Fall Time; VPF(MAX) to
VPF(MIN)tVCCF300µs
VCC Rise Time; VPF(MIN) to
VPF(MAX)tVCCR0µs
WARNING:Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode.
Note 1:Limits at -40°C are guaranteed by design and not production tested.
Note 2:All voltages are referenced to ground.
Note 3:Measured at VCC= typ, VBACKUP= 0V, register 08h = A5h.
Note 4:The use of the 250Ωtrickle-charge resistor is not allowed at VCC> 3.63V and should not be enabled.
Note 5:Measured at VCC= typ, VBACKUP= 0V, register 08h = A6h.
Note 6:Measured at VCC= typ, VBACKUP= 0V, register 08h = A7h.
Note 7:ICCA—SCL clocking at max frequency = 400kHz.
Note 8:Specified with I2C bus inactive.
Note 9:Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 10:Limits at +25°C are guaranteed by design and not production tested.
Note 11:After this period, the first clock pulse is generated.
Note 12:A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH(MIN)of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
Note 13:The maximum tHD:DATonly has to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 14:A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT≥to 250ns must be met. This
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line tR MAX+ tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 15:CB—total capacitance of one bus line in pF.
Note 16:The parameter tOSFis the period of time the oscillator must be stopped for the OSF flag to be set over the 0V ≤VCC≤
VCCMAXand 1.3V ≤VBAT≤ 3.7V range.
Note 17:This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay
occurs.
SCL
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).SDA
STOPSTARTREPEATED
START
tBUF
tHD:STA
tHD:DATtSU:DAT
tSU:STO
tHD:STAtSP
tSU:STAtHIGH
tLOW
DS1340I2C RTC with Trickle Charger
OUTPUTS
VCC
VPF(MAX)
INPUTS
HIGH-Z
DON'T CARE
VALID
RECOGNIZEDRECOGNIZED
VALID
VPF(MIN)
tRECtF
VPFVPF
Figure 2. Power-Up/Power-Down Timing
ICCSA vs. VCC FT = 0DS1340 toc01
VCC (V)
SUPPLY CURRENT (
ICCS vs. VCC FT = 0
DS1340 toc02
VCC (V)
SUPPLY CURRENT (
-1.8V
-3.0V
-3.3V
IBACKUP1 (FT = 0) vs. VBACKUPDS1340 toc03
VBACKUP (V)
SUPPLY CURRENT (nA)
IBACKUP2 (FT = 1) vs. VBACKUP
DS1340 toc04
VBACKUP (V)
SUPPLY CURRENT (nA)
IBACKUP3 vs. TEMPERATURE
DS1340 toc05
TEMPERATURE (°C)
SUPPLY CURRENT (nA)40-20020
VBACKUP = 3.0V
OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE
(FT x 64)DS1340 toc06
VBACKUP (V)
FREQUENCY (Hz)
Typical Operating Characteristics
(VCC= +3.3V, TA= +25°C, unless otherwise noted.)
DS1340I2C RTC with Trickle Charger
Detailed DescriptionThe DS1340 is a low-power clock/calendar with a trickle
charger. Address and data are transferred serially
through a I2C bidirectional bus. The clock/calendar pro-
vides seconds, minutes, hours, day, date, month, and
year information. The date at the end of the month is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The DS1340
has a built-in power-sense circuit that detects power fail-
ures and automatically switches to the backup supply.
Power ControlThe power-control function is provided by a precise,
temperature-compensated voltage reference and a
comparator circuit that monitors the VCClevel. The
device is fully accessible and data can be written and
read when VCCis greater than VPF. However, when VCC
from any access. If VPFis less than VBACKUP, the
device power is switched from VCCto VBACKUPwhen
VCCdrops below VPF. If VPFis greater than VBACKUP,
the device power is switched from VCCto VBACKUP
Pin Description
PIN
816NAMEFUNCTIONX1X2
Connections for a Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for
operation with a crystal having a specified load capacitance (CL) of 12.5pF. X1 is the input to the oscillator
and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator,
X2, is left unconnected if an external oscillator is connected to X1.
314VBACKUP
Connection for a Secondary Power Supply. For the 1.8V and 3V devices, VBACKUP must be held between
1.3V and 3.7V for proper operation. Diodes placed in series between the supply and the input pin may
result in improper operation. VBACKUP can be as high as 5.5V on the 3.3V device.
This pin can be connected to a primary cell such as a lithium coin cell. Additionally, this pin can be
connected to a rechargeable cell or a super cap when used with the trickle-charge feature. UL
recognized to ensure against reverse charging when used with a lithium battery
(www.maximintegrated.com/qa/info/ul).15GNDGround16SDASerial Data Input/Output. SDA is the data input/output for the I2C serial interface. The SDA pin is open
drain and requires an external pullup resistor.1SCLSerial Clock Input. SCL is the clock input for the I2C interface and is used to synchronize data movement
on the serial interface.2FT/OUT
Frequency Test/Output. This pin is used to output either a 512Hz signal or the value of the OUT bit. When
the FT bit is logic 1, the FT/OUT pin toggles at a 512Hz rate. When the FT bit is logic 0, the FT/OUT pin
reflects the value of the OUT bit. This open-drain pin requires an external pullup resistor, and operates
with either VCC or VBACKUP applied. The pullup voltage can be up to 5.5V, regardless of the voltage on
VCC. If not used, this pin can be left unconnected.VCC
Primary Power Supply. When voltage is applied within normal limits, the device is fully accessible and data
can be written and read. When a backup supply is connected to the device and VCC is below VPF, reads
and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage.4–13N.C.No Connection. Must be connected to ground.
SUPPLY CONDITION READ/WRITE
ACCESS
POWERED
BY VCC < VPF,
VCC < VBACKUPNo VBAT
VCC < VPF,
VCC > VBACKUPNo VCC
VCC > VPF,
VCC < VBACKUPYes VCC
VCC > VPF,
VCC > VBACKUPYes VCC
Table 1. Power Control
DS1340I2C RTC with Trickle Charger
when VCCdrops below VBACKUP. The registers are
maintained from the VBACKUPsource until VCCis
returned to nominal levels (Table 1). After VCCreturns
above VPF, read and write access is allowed tREC.
Oscillator CircuitThe DS1340 uses an external 32.768kHz crystal. The
oscillator circuit does not require any external resistors
or capacitors to operate. Table 2 specifies several crys-
tal parameters for the external crystal. Figure 3 shows a
functional schematic of the oscillator circuit. If using a
crystal with the specified characteristics, the startup
time is usually less than one second.
Clock AccuracyThe initial clock accuracy depends on the accuracy of
the crystal and the accuracy of the match between the
capacitive load of the oscillator circuit and the capaci-
tive load for which the crystal was trimmed. Additional
error is added by crystal frequency drift caused by
temperature shifts. External circuit noise coupled into
the oscillator circuit can result in the clock running fast.
Figure 4 shows a typical PC board layout for isolating
the crystal and oscillator from noise. Refer to
Application Note 58: Crystal Considerations with Dallas
Real-Time Clocks(www.maximintegrated.com/RTCapps)
for detailed information.
DS1340C OnlyThe DS1340C integrates a standard 32,768Hz crystal
into the package. Typical accuracy with nominal VCC
and +25°C is approximately +15ppm. Refer to
Application Note 58 for information about crystal accu-
racy vs. temperature.
OperationThe DS1340 operates as a slave device on the serial
bus. Access is obtained by implementing a START
condition and providing a device identification code fol-
lowed by data. Subsequent registers can be accessed
sequentially until a STOP condition is executed. The
device is fully accessible and data can be written and
read when VCCis greater than VPF. However, when
VCCfalls below VPF, the internal clock registers are
blocked from any access. If VPFis less than VBACKUP,
the device power is switched from VCCto VBACKUP
when VCCdrops below VPF. If VPFis greater than
VBACKUP, the device power is switched from VCCto
VBACKUPwhen VCCdrops below VBACKUP. The regis-
ters are maintained from the VBACKUPsource until VCC
is returned to nominal levels. The functional diagram
(Figure 5) shows the main elements of the serial RTC.
PARAMETERSYMBOLMINTYPMAXUNITSNominal
FrequencyfO32.768kHz
Series ResistanceESR80kΩ
Load CapacitanceCL12.5pF
Table 2. Crystal Specifications**The crystal, traces, and crystal input pins should be isolated
from RF generating signals. Refer to Application Note 58:
Crystal Considerations for Dallas Real-Time Clocksfor addi-
tional specifications.
COUNTDOWN
CHAIN
RTCX2
CL1CL2
CRYSTAL
RTC
REGISTERS
Figure 3. Oscillator Circuit Showing Internal Bias Network
CRYSTAL
GND
LOCAL GROUND PLANE (LAYER 2)
Figure 4. Layout Example
DS1340I2C RTC with Trickle Charger
Address MapTable 3 shows the DS1340 address map. The RTC reg-
isters are located in address locations 00h to 06h, and
the control register is located at 07h. The trickle-charge
and flag registers are located in address locations 08h
to 09h. During a multibyte access of the timekeeping
registers, when the address pointer reaches 07h—the
end of the clock and control register space—it wraps
around to location 00h. Writing the address pointer to
the corresponding location accesses address locations
08h and 09h. After accessing location 09h, the address
pointer wraps around to location 00h. On a I2CSTART,
STOP, or address pointer incrementing to location 00h,
the current time is transferred to a second set of regis-
ters. The time information is read from these secondary
registers, while the clock may continue to run. This
eliminates the need to reread the registers in case the
main registers update during a read.
Clock and CalendarThe time and calendar information is obtained by read-
ing the appropriate register bytes. Table 3 shows the
RTC registers. The time and calendar data are set or
initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the
binary-coded decimal (BCD) format. The day-of-week
ADDRESSBIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0FUNCTIONRANGE00HEOSC10 SecondsSecondsSeconds00–59
01HX10 MinutesMinutesMinutes00–59
02HCEBCB10 HoursHoursCentury/Hours0–1; 00–23
03HXXXXXDayDay01–07
04HXX10 DateDateDate01–31
05HXXX10 MonthMonthMonth01–12
06H10 YearYearYear00–99
07HOUTFTSCAL4CAL3CAL2CAL1CAL0Control—
08HTCS3TCS2TCS1TCS0DS1DS0ROUT1ROUT0Trickle Charger—
09HOSF0000000Flag—
Table 3. Address MapX = Read/Write bit
Note:Unless otherwise specified, the state of the registers is not defined when power is first applied.
SERIAL
INTERFACE
AND ADDRESS
REGISTER
CONTROL
LOGIC
"C" VERSION ONLY
SCL
SDA
512HzMUX/
BUFFER
FT/OUT
USER BUFFER
(7 BYTES)
CLOCK AND
CALENDAR
REGISTERS
32,768Hz
1Hz
POWER
CONTROL
VCC
VBACKUP
DIVIDER AND
CALIBRATION
CIRCUIT
DS1340
Figure 5. Functional Diagram
