DS1338U-33+ ,I²C RTC with 56-Byte NV RAMFEATURES The DS1338 serial real-time clock (RTC) is a low-• Completely Manages All Timekeeping powe ..
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DS1338C-33#-DS1338U-33+-DS1338U-33+T&R-DS1338Z-DS1338Z-18+-DS1338Z-33+-DS1338Z-33+T&R
I²C RTC with 56-Byte NV RAM
GENERAL DESCRIPTION The DS1338 serial real-time clock (RTC) is a low-
power, full binary-coded decimal (BCD)
clock/calendar plus 56 bytes of NV SRAM. Address
and data are transferred serially through an I2C
interface. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year
information. The end of the month date is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicator. The DS1338 has a built-in power-
sense circuit that detects power failures and
automatically switches to the backup supply,
maintaining time and date operation
APPLICATIONS Handhelds (GPS, POS Terminal)
Consumer Electronics (Set-Top Box, Digital
Recording, Network Appliance)
Office Equipment (Fax/Printer, Copier)
Medical (Glucometer, Medicine Dispenser)
Telecommunications (Router, Switcher, Server)
Other (Utility Meter, Vending Machine, Thermostat,
Modem)
UL is a registered trademark of Underwriters Laboratories Inc.
TYPICAL OPERATING CIRCUIT
BENEFITS AND FEATURES •
Completely Manages All Timekeeping
Functions RTC Counts Seconds, Minutes, Hours,
Date of the Month, Month, Day of the
Week, and Year with Leap-Year
Compensation Valid Up to 2100 56-Byte, Battery-Backed, General-
Purpose RAM with Unlimited Writes Programmable Square-Wave Output
Signal •
Surface-Mount Package with an Integrated
Crystal (DS1338C) Saves Additional Space
and Simplifies Design •
Interfaces with Most Microcontrollers I2C Serial Interface •
Low-Power Operation Extends Battery
Backup Run Time Automatic Power-Fail Detect and Switch
Circuitry •
-40°C to +85°C Industrial Temperature Range
Supports Operation in a Wide Range of
Applications •
Underwriters Laboratories (UL®) Recognized
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE TOP MARK† DS1338Z-18+ -40°C to +85°C 8 SO (0.150″) DS1338-18
DS1338Z-3+ -40°C to +85°C 8 SO (0.150″) DS1338-3
DS1338Z-33+ -40°C to +85°C 8 SO (0.150″) DS133833
DS1338U-18+ -40°C to +85°C 8 µSOP 1338
rr-18
DS1338U-3+ -40°C to +85°C 8 µSOP 1338
rr-3
DS1338U-33+ -40°C to +85°C 8 µSOP 1338
rr-33
DS1338C-18# -40°C to +85°C 16 SO (0.300″) DS1338C-18
DS1338C-3# -40°C to +85°C 16 SO (0.300″) DS1338C-3
DS1338C-33# -40°C to +85°C 16 SO (0.300″) DS1338C-33
rr = second line, revision level
+ Denotes a lead(Pb)-free/RoHS-compliant device.
# Denotes a RoHS-compliant device that may include lead that is
exempt under the RoHS requirements. The lead finish is JESD97
category e3, and is compatible with both lead-based and lead-free
soldering processes.
† A “+” anywhere on the top mark denotes a lead-free device. A “#”
denotes a RoHS-compliant device.
Pin Configurations appear at end of data sheet.
DS1338 CPU CC CC CC
SDA
SCL
GND
X2 X1 CC PU R PU
CRYSTAL
SQW/OUT BAT PU = t r /C b
DS1338 2C RTC with 56-Byte NV RAM ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground………………………………………………………..……..-0.3V to +6.0V
Operating Temperature Range…………………………………………………………………………..……-40°C to +85°C
Storage Temperature Range………………………………………………………………………………...-55°C to +125°C
Lead Temperature (soldering, 10s) ……….………………………………………………………………………. +260°C
Soldering Temperature (reflow) ……………………………………………………………………………………. +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, unless
otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC
DS1338-18 1.71 1.8 5.5 DS1338-3 2.7 3.0 5.5
DS1338-33 3.0 3.3 5.5
Logic 1 VIH (Note 2) 0.7 x
VCC VCC +
0.3 V
Logic 0 VIL (Note 2) -0.3 +0.3 x
VCC V
Power-Fail Voltage VPF
DS1338-18 1.51 1.62 1.71 DS1338-3 2.45 2.59 2.70
DS1338-33 2.70 2.82 2.97
VBAT Input Voltage VBAT (Note 2) 1.3 3.0 3.7 V
DC ELECTRICAL CHARACTERISTICS (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = TYP,
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage ILI (Note 3) 1 µA
I/O Leakage ILO (Note 4) 1 µA
SDA Logic 0 Output IOLSDA VCC > 2V; VOL = 0.4V 3.0 mA VCC < 2V; VOL = 0.2 x VCC 3.0
SQW/OUT Logic 0 Output IOLSQW
VCC > 2V; VOL = 0.4V 3.0
mA 1.71V < VCC < 2V;
VOL = 0.2 x VCC 3.0
1.3V < VCC < 1.71V;
VOL = 0.2 x VCC 250 µA
Active Supply Current
(Note 5) ICCA
DS1338-18: VCC = 1.89V 75 150 µA DS1338-3: VCC = 3.30V 110 200
DS1338-33 VCC = 3.63V 120 200
VCC = 5.5V 325
Standby Current (Note 6) ICCS
DS1338-18: VCC = 1.89V 60 100 µA DS1338-3: VCC = 3.30V 80 125
DS1338-33 VCC = 3.63V 85 125
VCC = 5.5V 200
VBAT Leakage Current
(VCC Active) IBATLKG 25 100 nA
DS1338
DC ELECTRICAL CHARACTERISTICS (VCC = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VBAT = 3.0V, TA = +25°C, unless
otherwise noted.) (Note 1)
PARAMETER SYMBOL MIN TYP MAX UNITS VBAT Current (OSC ON); VBAT = 3.7V, SQW/OUT OFF (Note 7) IBATOSC1 800 1200 nA
VBAT Current (OSC ON); VBAT = 3.7V, SQW/OUT ON (32kHz)
(Note 7) IBATOSC2 1025 1400 nA
VBAT Data-Retention Current (Osc Off); VBAT = 3.7V (Note 7) IBATDAT 10 100 nA
AC ELECTRICAL CHARACTERISTICS (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C) (Note 1)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS SCL Clock Frequency fSCL Fast mode 100 400 kHz Standard mode 0 100
Bus Free Time Between STOP
and START Condition tBUF Fast mode 1.3 µs Standard mode 4.7
Hold Time (Repeated) START
Condition (Note 8) tHD:STA Fast mode 0.6 µs Standard mode 4.0
LOW Period of SCL Clock tLOW Fast mode 1.3 µs Standard mode 4.7
HIGH Period of SCL Clock tHIGH Fast mode 0.6 µs Standard mode 4.0
Setup Time for Repeated
START Condition tSU:STA Fast mode 0.6 µs Standard mode 4.7
Data Hold Time (Notes 9, 10) tHD:DAT Fast mode 0 0.9 µs Standard mode 0
Data Setup Time (Note 11) tSU:DAT Fast mode 100 ns Standard mode 250
Rise Time of Both SDA and
SCL Signals (Note 12) tR Fast mode 20 + 0.1CB 300 ns Standard mode 20 + 0.1CB 1000
Fall Time of Both SDA and
SCL Signals (Note 12) tF Fast mode 20 + 0.1CB 300 ns Standard mode 20 + 0.1CB 300
Setup Time for STOP
Condition tSU:STO Fast mode 0.6 µs Standard mode 4.0
Capacitive Load for Each Bus
Line CB (Note 12) 400 pF
I/O Capacitance (SDA, SCL) CI/O (Note 13) 10 pF
Oscillator Stop Flag (OSF)
Delay tOSF (Note 14) 100 ms
DS1338
POWER-UP/POWER-DOWN CHARACTERISTICS (TA = -40°C to +85°C) (Note 1, Figure 1)
PARAMETER SYMBOL MIN TYP MAX UNITS Recovery at Power-Up (Note 15) tREC 2 ms
VCC Fall Time; VPF(MAX) to VPF(MIN) tVCCF 300 µs
VCC Rise Time; VPF(MIN) to VPF(MAX) tVCCR 0 µs
Warning: Negative undershoots below -0.3V while the part is in battery-backed mode may cause
loss of data.
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: All voltages are referenced to ground.
Note 3: SCL only.
Note 4: SDA and SQW/OUT.
Note 5: ICCA—SCL clocking at max frequency = 400kHz.
Note 6: Specified with the I2C bus inactive.
Note 7: Measured with a 32.768kHz crystal attached to X1 and X2.
Note 8: After this period, the first clock pulse is generated.
Note 9: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 10: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 11: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line
is released.
Note 12: CB—total capacitance of one bus line in pF.
Note 13: Guaranteed by design. Not production tested.
Note 14: The parameter tOSF is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤ VCC ≤ VCC(MAX) and 1.3V ≤ VBAT ≤ 3.7V.
Note 15: This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs.
Figure 1. Power-Up/Power-Down Timing OUTPUTS
VCC V PF(MAX) PF(MIN)
INPUTS
HIGH-Z
DON'T CARE
VALID
RECOGNIZED RECOGNIZED
VALID VCCF t VCCR REC
DS1338
Figure 2. Timing Diagram
Figure 3. Block Diagram RAM
(56 X 8)
SERIAL BUS
INTERFACE
AND ADDRESS
REGISTER
CONTROL
LOGIC
1Hz
1Hz/4.096kHz/8.192kHz/32.768kHzMUX/
BUFFER
USER BUFFER
(7 BYTES)
CLOCK,
CALENDAR,
AND CONTROL
REGISTERS
"C" VERSION ONLY
POWER
CONTROL
DS1338X2
SDA
SCL
SQW/OUTCC
GNDBAT
Oscillator
and divider
DS1338
TYPICAL OPERATING CHARACTERISTICS
IBAT vs. VBATVBAT (V)
CURRE
VCC=0V
RS1=RS0=1
IBATOSC2
(SQWE = 1)
IBATOSC1
(SQWE = 0)
IBAT vs. Temperature
VBAT = 3.0VTEMPERATURE (°C)
CURRE
VCC=0V
SQWE=1
SQWE=0
ICC vs. VCCVCC (V)
CURRE
SCL=400kHz
SCL=SDA=0Hz
Oscillator Frequency vs. Supply VoltageOscillator Supply Voltage (V)
NCY
DS1338
PIN DESCRIPTION
PIN NAME FUNCTION 8 16 — X1
32.768kHz Crystal Connections. The internal oscillator circuitry is designed for
operation with a crystal having a specified load capacitance (CL) of 12.5pF. An
external 32.768kHz oscillator can also drive the DS1338. In this configuration,
the X1 pin is connected to the external oscillator signal and the X2 pin is left
unconnected.
Note: For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. — X2 14 VBAT
Backup Supply Input for Lithium Cell or Other Energy Source. Battery voltage
must be held between the minimum and maximum limits for proper operation.
Diodes placed in series between the backup source and the VBAT pin may
prevent proper operation. If a backup supply is not required, VBAT must be
grounded. UL recognized to ensure against reverse charging when used with a
lithium cell. For more information, visit /qa/info/ul. 15 GND
Ground. DC power is provided to the device on these pins. VCC is the primary
power input. When voltage is applied within normal limits, the device is fully
accessible and data can be written and read. When a backup supply is
connected to the device and VCC is below VPF, reads and writes are inhibited.
However, the timekeeping function continues unaffected by the lower input
voltage. 16 SDA
Serial Data. Input/output pin for the I2C serial interface. It is an open drain
output and requires an external pullup resistor. The pull up voltage may be up
to 5.5V regardless of the voltage on VCC. 1 SCL
Serial Clock. Input pin for the I2C serial interface. Used to synchronize data
movement on the serial interface. The pull up voltage may be up to 5.5V
regardless of the voltage on VCC. 2 SQW/OUT
Square-Wave/Output Driver. When enabled and the SQWE bit set to 1, the
SQW/OUT pin outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz,
32kHz). It is an open drain output and requires an external pullup resistor.
Operates with either VCC or VBAT applied. The pull up voltage may be up to
5.5V regardless of the voltage on VCC. If not used, this pin may be left
unconnected. 3 VCC
Primary Power Supply. When voltage is applied within normal limits, the device
is fully accessible and data can be written and read. When a backup supply is
connected to the device and VCC is below VPF, reads and writes are inhibited.
The backup supply maintains the timekeeping function while VCC is absent. 4–13 N.C. No Connection. These pins are not connected internally, but must be grounded
for proper operation.
DETAILED DESCRIPTION The DS1338 serial RTC is a low-power, full BCD clock/calendar plus 56 bytes of NV SRAM. Address and data are
transferred serially through an I2C interface. The clock/calendar provides seconds, minutes, hours, day, date,
month, and year information. The end of the month date is automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM
indicator. The DS1338 has a built-in power-sense circuit that detects power failures and automatically switches to
the VBAT supply.
DS1338
OPERATION The DS1338 operates as a slave device on the serial bus. Access is obtained by implementing a START condition
and providing a device identification code, followed by data. Subsequent registers can be accessed sequentially
until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is
greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If
VPF is less than VBAT, the device power is switched from VCC to VBAT when VCC drops below VPF. If VPF is greater
than VBAT, the device power is switched from VCC to VBAT when VCC drops below VBAT. The oscillator and
timekeeping functions are maintained from the VBAT source until VCC is returned to nominal levels. The block
diagram (Figure 3) shows the main elements of the DS1338.
An enable bit in the seconds register controls the oscillator. Oscillator startup times are highly dependent upon
crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major
contributors to long start-up times. A circuit using a crystal with the recommended characteristics and proper layout
usually starts within 1 second.
POWER CONTROL The power-control function is provided by a precise, temperature-compensated voltage reference and a
comparator circuit that monitors the VCC level. The device is fully accessible and data can be written and read when
VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any
access. If VPF is less than VBAT, the device power is switched from VCC to VBAT when VCC drops below VPF. If VPF is
greater than VBAT, the device power is switched from VCC to VBAT when VCC drops below VBAT. The registers are
maintained from the VBAT source until VCC is returned to nominal levels (Table 1). After VCC returns above VPF, read
and write access is allowed after tREC (Figure 1). On the first application of power to the device the time and date
registers are reset to 01/01/00 01 00:00:00 (DD/MM/YY DOW HH:MM:SS). The CH bit in the seconds register will be set
to a 0.
Table 1. Power Control
SUPPLY
CONDITION
READ/WRITE
ACCESS
POWERED
BY VCC < VPF, VCC < VBAT No VBAT
VCC < VPF, VCC > VBAT No VCC
VCC > VPF, VCC < VBAT Yes VCC
VCC > VPF, VCC > VBAT Yes VCC
OSCILLATOR CIRCUIT The DS1338 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or
capacitors to operate. Table 2 specifies several crystal parameters for the external crystal. Figure 3 shows a
functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal
with the specified characteristics.
Table 2. Crystal Specifications*
PARAMETER SYMBOL MIN TYP MAX UNITS Nominal Frequency fO 32.768 kHz
Series Resistance ESR 50 kΩ
Load Capacitance CL 12.5 pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to
Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
