DS1307 ,64 x 8 Serial Real Time Clockblock diagram in Figure 1 shows theCC BATmain elements of the serial RTC.DS1307
DS1307 ,64 x 8 Serial Real Time ClockDS130764 x 8 Serial Real-Time Clock
DS1307 ,64 x 8 Serial Real Time ClockPIN DESCRIPTION Available in 8-pin DIP or SOICV - Primary Power SupplyCC Underwriters Laboratory ..
DS1307 ,64 x 8 Serial Real Time ClockFEATURES PIN ASSIGNMENT Real-time clock (RTC) counts seconds,l 8 VX1 CCminutes, hours, date of the ..
DS1307 ,64 x 8 Serial Real Time Clockblock diagram in Figure 1 shows theCC BATmain elements of the serial RTC.DS1307
DS1307 ,64 x 8 Serial Real Time ClockFEATURES PIN ASSIGNMENT Real-time clock (RTC) counts seconds,l 8 VX1 CCminutes, hours, date of the ..
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DTC123JCA ,Conductor Holdings Limited - Digital Transistor
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DS1307
64 x 8 Serial Real Time Clock
FEATURESReal-time clock (RTC) counts seconds,
minutes, hours, date of the month, month, day
of the week, and year with leap-year
compensation valid up to 210056-byte, battery-backed, nonvolatile (NV)
RAM for data storageTwo-wire serial interfaceProgrammable squarewave output signalAutomatic power-fail detect and switchcircuitryConsumes less than 500nA in battery backup
mode with oscillator runningOptional industrial temperature range:
-40°C to +85°CAvailable in 8-pin DIP or SOICUnderwriters Laboratory (UL) recognized
ORDERING INFORMATIONDS1307 8-Pin DIP (300-mil)DS1307Z 8-Pin SOIC (150-mil)
DS1307N 8-Pin DIP (Industrial)
DS1307ZN 8-Pin SOIC (Industrial)
PIN ASSIGNMENT
PIN DESCRIPTIONVCC - Primary Power Supply
X1, X2 - 32.768kHz Crystal Connection
VBAT - +3V Battery InputGND - Ground
SDA - Serial Data
SCL - Serial Clock
SQW/OUT - Square Wave/Output Driver
DESCRIPTIONThe DS1307 Serial Real-Time Clock is a low-power, full binary-coded decimal (BCD) clock/calendar
plus 56 bytes of NV SRAM. Address and data are transferred serially via a 2-wire, bi-directional bus.
The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end ofthe month date is automatically adjusted for months with fewer than 31 days, including corrections for
leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The
DS1307 has a built-in power sense circuit that detects power failures and automatically switches to the
battery supply.
DS1307
64 x 8 Serial Real-Time ClockVBAT
GND
VCC
SQW/OUT
SCL
SDA
DS1307
OPERATIONThe DS1307 operates as a slave device on the serial bus. Access is obtained by implementing a STARTcondition and providing a device identification code followed by a register address. Subsequent registers
can be accessed sequentially until a STOP condition is executed. When VCC falls below 1.25 x VBAT the
device terminates an access in progress and resets the device address counter. Inputs to the device will
not be recognized at this time to prevent erroneous data from being written to the device from an out of
tolerance system. When VCC falls below VBAT the device switches into a low-current battery backupmode. Upon power-up, the device switches from battery to VCC when VCC is greater than VBAT + 0.2V
and recognizes inputs when VCC is greater than 1.25 x VBAT. The block diagram in Figure 1 shows the
main elements of the serial RTC.
DS1307 BLOCK DIAGRAM Figure 1
DS1307
SIGNAL DESCRIPTIONS
VCC, GND – DC power is provided to the device on these pins. VCC is the +5V input. When 5V is
applied within normal limits, the device is fully accessible and data can be written and read. When a 3V
battery is connected to the device and VCC is below 1.25 x VBAT, reads and writes are inhibited. However,
the timekeeping function continues unaffected by the lower input voltage. As VCC falls below VBAT the
RAM and timekeeper are switched over to the external power supply (nominal 3.0V DC) at VBAT.
VBAT – Battery input for any standard 3V lithium cell or other energy source. Battery voltage must beheld between 2.0V and 3.5V for proper operation. The nominal write protect trip point voltage at which
access to the RTC and user RAM is denied is set by the internal circuitry as 1.25 x VBAT nominal. A
lithium battery with 48mAhr or greater will back up the DS1307 for more than 10 years in the absence ofpower at 25ºC. UL recognized to ensure against reverse charging current when used in conjunction with a
lithium battery.
See “Conditions of Acceptability” at http:///TechSupport/QA/ntrl.htm.
SCL (Serial Clock Input) – SCL is used to synchronize data movement on the serial interface.
SDA (Serial Data Input/Output) – SDA is the input/output pin for the 2-wire serial interface. The SDApin is open drain which requires an external pullup resistor.
SQW/OUT (Square Wave/Output Driver) – When enabled, the SQWE bit set to 1, the SQW/OUT pinoutputs one of four square wave frequencies (1Hz, 4kHz, 8kHz, 32kHz). The SQW/OUT pin is open
drain and requires an external pull-up resistor. SQW/OUT will operate with either Vcc or Vbat applied.
X1, X2 – Connections for a standard 32.768kHz quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF.
For more information on crystal selection and crystal layout considerations, please consult Application
Note 58, “Crystal Considerations with Dallas Real-Time Clocks.” The DS1307 can also be driven by an
external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator
signal and the X2 pin is floated.
DS1307
CLOCK ACCURACYThe accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit may result in the clock running fast. See Application Note58, “Crystal Considerations with Dallas Real-Time Clocks” for detailed information.
Please review Application Note 95, “Interfacing the DS1307 with a 8051-Compatible Microcontroller”
for additional information.
RTC AND RAM ADDRESS MAPThe address map for the RTC and RAM registers of the DS1307 is shown in Figure 2. The RTC registersare located in address locations 00h to 07h. The RAM registers are located in address locations 08h to
3Fh. During a multi-byte access, when the address pointer reaches 3Fh, the end of RAM space, it wraps
around to location 00h, the beginning of the clock space.
DS1307 ADDRESS MAP Figure 2
CLOCK AND CALENDARThe time and calendar information is obtained by reading the appropriate register bytes. The RTC
registers are illustrated in Figure 3. The time and calendar are set or initialized by writing the appropriateregister bytes. The contents of the time and calendar registers are in the BCD format. Bit 7 of register 0
is the clock halt (CH) bit. When this bit is set to a 1, the oscillator is disabled. When cleared to a 0, the
oscillator is enabled.
Please note that the initial power-on state of all registers is not defined. Therefore, it is important
to enable the oscillator (CH bit = 0) during initial configuration.The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is
the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10 hour bit (20-
23 hours).
On a 2-wire START, the current time is transferred to a second set of registers. The time information isread from these secondary registers, while the clock may continue to run. This eliminates the need to re-
read the registers in case of an update of the main registers during a read.
DS1307
DS1307 TIMEKEEPER REGISTERS Figure 3
CONTROL REGISTERThe DS1307 control register is used to control the operation of the SQW/OUT pin.
OUT (Output control): This bit controls the output level of the SQW/OUT pin when the square waveoutput is disabled. If SQWE = 0, the logic level on the SQW/OUT pin is 1 if OUT = 1 and is 0 ifOUT = 0.
SQWE (Square Wave Enable): This bit, when set to a logic 1, will enable the oscillator output. Thefrequency of the square wave output depends upon the value of the RS0 and RS1 bits. With the square
wave output set to 1Hz, the clock registers update on the falling edge of the square wave.
RS (Rate Select): These bits control the frequency of the square wave output when the square wave
output has been enabled. Table 1 lists the square wave frequencies that can be selected with the RS bits.
SQUAREWAVE OUTPUT FREQUENCY Table 1
DS1307
2-WIRE SERIAL DATA BUSThe DS1307 supports a bi-directional, 2-wire bus and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that
controls the message is called a master. The devices that are controlled by the master are referred to as
slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the
bus access, and generates the START and STOP conditions. The DS1307 operates as a slave on the 2-wire bus. A typical bus configuration using this 2-wire protocol is show in Figure 4.
TYPICAL 2-WIRE BUS CONFIGURATION Figure 4Figures 5, 6, and 7 detail how data is transferred on the 2-wire bus.Data transfer may be initiated only when the bus is not busy.During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes inthe data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,defines a START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line isHIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data lineis stable for the duration of the HIGH period of the clock signal. The data on the line must be changedduring the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with aninth bit. Within the 2-wire bus specifications a regular mode (100kHz clock rate) and a fast mode
(400kHz clock rate) are defined. The DS1307 operates in the regular mode (100kHz) only.
