DS1306EN-DS1306N Fast Delivery |IC PHOENIX CO.,LIMITED

DS1306EN ,Serial Alarm Real Time Clock (RTC)block diagram in Figure 1 shows the main elements of the Serial Alarm RTC. The followingparagraphs ..
DS1306EN ,Serial Alarm Real Time Clock (RTC)PIN DESCRIPTIONV – Primary Power SupplyCC1ORDERING INFORMATIONV – Backup Power SupplyCC2DS1306 16-P ..
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DS1306EN-DS1306N
Serial Alarm Real Time Clock (RTC)
FEATURESReal time clock counts seconds, minutes,
hours, date of the month, month, day of the
week, and year with leap year compensation
valid up to 210096-byte nonvolatile RAM for data storageTwo Time of Day Alarms - programmable on
combination of seconds, minutes, hours, and
day of the week1 Hz and 32.768 kHz clock outputsSerial interface supports Motorola Serial
Peripheral Interface (SPI) serial data ports or
standard 3-wire interfaceBurst Mode for reading/writing successive
addresses in clock/RAMDual power supply pins for primary and
backup power suppliesOptional trickle charge output to backup
supply2.0 - 5.5V operationOptional industrial temperature range
-40°C to +85°CAvailable in space-efficient 20-pin TSSOP
packageRecognized by Underwriters Laboratory
ORDERING INFORMATION
DS1306 16-Pin DIP
DS1306N 16-Pin DIP (Industrial)
DS1306E 20-Pin TSSOP
DS1306EN 20-Pin TSSOP (Industrial)
PIN ASSIGNMENT
PIN DESCRIPTION
VCC1 – Primary Power Supply
VCC2 – Backup Power Supply
VBAT – +3V Battery Input
VCCIF – Interface Logic Power Supply Input
GND – Ground
X1, X2 – 32.768 kHz Crystal Connection
INT0 – Interrupt 0 Output
INT1 – Interrupt 1 Output
SDI – Serial Data InSDO – Serial Data Out
CE – Chip Enable
SCLK – Serial Clock
SERMODE – Serial Interface Mode
1 Hz - 1 Hz Output
DS1306
Serial Alarm Real Time Clock (RTC)
VCC2
VBAT
INT0
INT1
1 Hz
GND
VCC1
32 kHz
VCCIF
SDO
SDI
SCLK
SERMODE
VCC2
DS1306 16-Pin DIP (300 mil)
INT0
1 Hz
GND
VCC1
SDO
SDI
SCLK
SERMODE
VBAT
INT1
32 kHz
VCCIF
DS1306
DESCRIPTION
The DS1306 Serial Alarm Real Time Clock provides a full BCD clock calendar which is accessed via a
simple serial interface. The clock/calendar provides seconds, minutes, hours, day, date, month, and year
information. The end of the month date is automatically adjusted for months with less than 31 days,
including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with
AM/PM indicator. In addition 96 bytes of nonvolatile RAM are provided for data storage.
An interface logic power supply input pin (VCCIF) allows the DS1306 to drive SDO and 32 kHz pins to a
level that is compatible with the interface logic. This allows an easy interface to 3-volt logic in mixed
supply systems. The DS1306 offers dual power supplies as well as a battery input pin. The dual power
supplies support a programmable trickle charge circuit which allows a rechargeable energy source (suchas a super cap or rechargeable battery) to be used for a backup supply. The VBAT pin allows the device to
be backed up by a non-rechargeable battery. The DS1306 is fully operational from 2.0 to 5.5 volts.
Two programmable time of day alarms are provided by the DS1306. Each alarm can generate an
interrupt on a programmable combination of seconds, minutes, hours, and day. “Don’t care” states can beinserted into one or more fields if it is desired for them to be ignored for the alarm condition. A 1 Hz and
a 32 kHz clock output are also available.
The DS1306 supports a direct interface to Motorola SPI serial data ports or standard 3-wire interface. An
easy-to-use address and data format is implemented in which data transfers can occur 1 byte at a time orin multiple-byte burst mode.
OPERATION
The block diagram in Figure 1 shows the main elements of the Serial Alarm RTC. The following
paragraphs describe the function of each pin.
DS1306 BLOCK DIAGRAM Figure 1
DS1306
SIGNAL DESCRIPTIONS
VCC1 - DC power is provided to the device on this pin. VCC1 is the primary power supply.
VCC2 - This is the secondary power supply pin. In systems using the trickle charger, the rechargeable
energy source is connected to this pin.
VBAT - Battery input for any standard 3-volt lithium cell or other energy source.
VCCIF (Interface Logic Power Supply Input) - The VCCIF pin allows the DS1306 to drive SDO and
32 kHz output pins to a level that is compatible with the interface logic, thus allowing an easy interface to
3-volt logic in mixed supply systems. This pin is physically connected to the source connection of the p-channel transistors in the output buffers of the SDO and 32 kHz pins.
SERMODE (Serial Interface Mode Input) - The SERMODE pin offers the flexibility to choosebetween two serial interface modes. When connected to GND, standard 3-wire communication is
selected. When connected to VCC, Motorola SPI communication is selected.
SCLK (Serial Clock Input) - SCLK is used to synchronize data movement on the serial interface foreither the SPI or 3-wire interface.
SDI (Serial Data Input) - When SPI communication is selected, the SDI pin is the serial data input for
the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDO pin (the SDI and
SDO pins function as a single I/O pin when tied together).
SDO (Serial Data Output) - When SPI communication is selected, the SDO pin is the serial data output
for the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDI pin (the SDIand SDO pins function as a single I/O pin when tied together).
CE (Chip Enable) - The Chip Enable signal must be asserted high during a read or a write for both
3-wire and SPI communication. This pin has an internal 55k pull-down resistor (typical).
INT0 (Interrupt 0 Output) - The INT0 pin is an active low output of the DS1306 that can be used as an
interrupt input to a processor. The INT0 pin can be programmed to be asserted by Alarm 0. The INT0
pin remains low as long as the status bit causing the interrupt is present and the corresponding interrupt
enable bit is set. The INT0 pin operates when the DS1306 is powered by VCC1, VCC2, or VBAT. The INT0
pin is an open drain output and requires an external pullup resistor.
1 Hz (1 Hz Clock Output) - The 1 Hz pin provides a 1 Hz squarewave output. This output is active
when the 1 Hz bit in the control register is a logic 1.
Both INT0 and 1 Hz pins are open drain outputs. The interrupt, 1 Hz signal, and the internal clock
continue to run regardless of the level of VCC (as long as a power source is present).
INT1 (Interrupt 1 Output) - The INT1 pin is an active high output of the DS1306 that can be used as aninterrupt input to a processor. The INT1 pin can be programmed to be asserted by alarm 1. When an
alarm condition is present, the INT1 pin generates a 62.5 ms active high pulse. The INT1 pin operates
only when the DS1306 is powered by VCC2 or VBAT. When active, the INT1 pin is internally pulled up to
DS1306
32 kHz (32.768 kHz Clock Output) - The 32 kHz pin provides a 32.768 kHz output. This signal is
always present.
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator is designed for
operation with a crystal having a specified load capacitance of 6 pF. For more information on crystal
selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations
with Dallas Real Time Clocks.” The DS1306 can also be driven by an external 32.768 kHz oscillator. In
this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
RTC AND RAM ADDRESS MAP
The address map for the RTC and RAM registers of the DS1306 is shown in Figure 2. Data is written to
the RTC by writing to address locations 80h to 9Fh and is written to the RAM by writing to address
locations A0h to FFh. RTC data is read by reading address locations 00h to 1Fh and RAM data is read by
reading address locations 20h to 7Fh.
ADDRESS MAP Figure 2
DS1306
CLOCK, CALENDAR, AND ALARM
The time and calendar information is obtained by reading the appropriate register bytes. The real time
clock registers are illustrated in Figure 3. The time, calendar, and alarm are set or initialized by writing
the appropriate register bytes. Note that some bits are set to 0. These bits will always read 0 regardless
of how they are written. Also note that registers 12h to 1Fh (read) and registers 92h to 9Fh are reserved.
These registers will always read 0 regardless of how they are written. The contents of the time, calendar,and alarm registers are in the Binary-Coded Decimal (BCD) format.
RTC REGISTERS Figure 3
RTC REGISTERS DS1306
Alarm 1
NOTE:
Range for alarm registers does not include mask’m’ bits.
DS1306
The DS1306 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is
the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23
hours).
The DS1306 contains two time of day alarms. Time of Day Alarm 0 can be set by writing to registers
87h to 8Ah. Time of Day Alarm 1 can be set by writing to registers 8Bh to 8Eh. Bit 7 of each of the time
of day alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, a time of day alarm
will only occur once per week when the values stored in timekeeping registers 00h to 03h match thevalues stored in the time of day alarm registers. An alarm will be generated every day when bit 7 of the
day alarm register is set to a logic 1. An alarm will be generated every hour when bit 7 of the day and
hour alarm registers is set to a logic 1. Similarly, an alarm will be generated every minute when bit 7 of
the day, hour, and minute alarm registers is set to a logic 1. When bit 7 of the day, hour, minute, and
seconds alarm registers is set to a logic 1, an alarm will occur every second.
TIME OF DAY ALARM MASK BITS Table 1
SPECIAL PURPOSE REGISTERS
The DS1306 has three additional registers (Control Register, Status Register, and Trickle Charger
Register) that control the real time clock, interrupts, and trickle charger.
CONTROL REGISTER (READ 0FH, WRITE 8FH)
WP (Write Protect) - Before any write operation to the clock or RAM, this bit must be logic 0. When
high, the write protect bit prevents a write operation to any register, including bits 0, 1, and 2 of the
control register. Upon initial power up, the state of the WP bit is undefined. Therefore the WP bit should
be cleared before attempting to write to the device.
1 Hz (1 Hz output enable) - This bit controls the 1 Hz output. When this bit is a logic 1, the 1 Hz output
is enabled. When this bit is a logic 0, the 1 Hz output is high Z.
AIE0 (Alarm Interrupt Enable 0) - When set to a logic 1, this bit permits the Interrupt 0 Request Flag
(IRQF0) bit in the status register to assert INT0. When the AIE0 bit is set to logic 0, the IRQF0 bit does
not initiate the INT0 signal.
AIE1 (Alarm Interrupt Enable 1) - When set to a logic 1, this bit permits the Interrupt 1 Request Flag
(IRQF1) bit in the status register to assert INT1. When the AIE1 bit is set to logic 0, the IRQF1 bit does
DS1306
STATUS REGISTER (READ 10H)
IRQF0 (Interrupt 0 Request Flag) - A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the Alarm 0 registers. If the AIE0 bit is also a logic 1, the INT0 pin will go low.
IRQF0 is cleared when any of the Alarm 0 registers are read or written.
IRQF1 (Interrupt 1 Request Flag) - A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the Alarm 1 registers. If the AIE1 bit is also a logic 1, the INT1 pin will generate a
62.5- ms active high pulse. IRQF1 is cleared when any of the Alarm 1 registers are read or written.
TRICKLE CHARGE REGISTER (READ 11H, WRITE 91H)
This register controls the trickle charge characteristics of the DS1306. The simplified schematic of
Figure 4 shows the basic components of the trickle charger. The trickle charge select (TCS) bits (bits4-7) control the selection of the trickle charger. In order to prevent accidental enabling, only a pattern of
1010 will enable the trickle charger. All other patterns will disable the trickle charger. The DS1306
powers up with the trickle charger disabled. The diode select (DS) bits (bits 2-3) select whether one
diode or two diodes are connected between VCC1 and VCC2. If DS is 01, one diode is selected. If DS is10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled independently of TCS. The
RS bits select the resistor that is connected between VCC1 and VCC2. The resistor is selected by the
resistor select (RS) bits as shown in Table 2.
PROGRAMMABLE TRICKLE CHARGER Figure 4
DS1306
TRICKLE CHARGER RESISTOR SELECT Table 2
If RS is 00, the trickle charger is disabled independently of TCS.
Diode and resistor selection is determined by the user according to the maximum current desired for
battery or super cap charging. The maximum charging current can be calculated as illustrated in the
following example. Assume that a system power supply of 5 volts is applied to VCC1 and a super cap is
connected to VCC2. Also assume that the trickle charger has been enabled with one diode and resister R1
between VCC1 and VCC2. The maximum current I MAX would therefore be calculated as follows:IMAX = (5.0V - diode drop)/R1
~ (5.0V - 0.7V)/2 kΩ
~ 2.2 mA
Obviously, as the super cap charges, the voltage drop between VCC1 and VCC2 will decrease and thereforethe charge current will decrease.
POWER CONTROL
Power is provided through the VCC1, VCC2, and VBAT pins. Three different power supply configurations
are illustrated in Figure 5. Configuration 1 shows the DS1306 being backed up by a non-rechargeable
energy source such as a lithium battery. In this configuration, the system power supply is connected toVCC1 and VCC2 is grounded. The DS1306 will be write-protected if VCC1 is less than VBAT.
Configuration 2 illustrates the DS1306 being backed up by a rechargeable energy source. In this case, the
VBAT pin is grounded, VCC1 is connected to the primary power supply, and VCC2 is connected to the
secondary supply (the rechargeable energy source). The DS1306 will operate from the larger of VCC1 orVCC2. When VCC1 is greater than VCC2 + 0.2 volt (typical), VCC1 will power the DS1306. When VCC1 is
less than VCC2, VCC2 will power the DS1306. The DS1306 does not write-protect itself in this
configuration.
Configuration 3 shows the DS1306 in battery operate mode where the device is powered only by a singlebattery. In this case, the VCC1 and VBAT pins are grounded and the battery is connected to the VCC2 pin.
Only these three configurations are allowed. Unused supply pins must be grounded.
SERIAL INTERFACE
The DS1306 offers the flexibility to choose between two serial interface modes. The DS1306 can
communicate with the SPI interface or with a standard 3-wire interface. The interface method used is
determined by the SERMODE pin. When this pin is connected to VCC, SPI communication is selected.
When this pin is connected to ground, standard 3-wire communication is selected.
SERIAL PERIPHERAL INTERFACE (SPI)The serial peripheral interface (SPI) is a synchronous bus for address and data transfer and is used when
DS1306
Four pins are used for the SPI. The four pins are the SDO (Serial Data Out), SDI (Serial Data In), CE
(Chip Enable), and SCLK (Serial Clock). The DS1306 is the slave device in an SPI application, with the
microcontroller being the master.
The SDI and SDO pins are the serial data input and output pins for the DS1306, respectively. The CE
input is used to initiate and terminate a data transfer. The SCLK pin is used to synchronize data
movement between the master (microcontroller) and the slave (DS1306) devices.
The shift clock (SCLK), which is generated by the microcontroller, is active only during address and datatransfer to any device on the SPI bus. The inactive clock polarity is programmable in some
microcontrollers. The DS1306 offers an important feature in that the level of the inactive clock is
determined by sampling SCLK when CE becomes active. Therefore either SCLK polarity can be
accommodated. Input data (SDI) is latched on the internal strobe edge and output data (SDO) is shifted
out on the shift edge (see Table 3 and Figure 6). There is one clock for each bit transferred. Address anddata bits are transferred in groups of eight.
POWER SUPPLY CONFIGURATIONS FOR THE DS1306 Figure 5
Configuration 1: Backup Supply is a Non-Rechargeable Lithium Battery
Configuration 2: Backup Supply is a Rechargeable Battery or Super Capacitor
Configuration 3: Battery Operate Mode
DS1306
FUNCTION TABLE Table 3CPOL is the “Clock Polarity” bit that is set in the control register of the microcontroller.SDO remains at High Z until 8 bits of data are ready to be shifted out during a read.
NOTE:
CPHA bit polarity (if applicable) may need to be set accordingly.
SERIAL CLOCK AS A FUNCTION OF MICROCONTROLLER
CLOCK POLARITY (CPOL) Figure 6

Partno	Mfg	Dc	Qty	Available	Descript
DS1306EN	DALLAS	N/a	5000	avai	Serial Alarm Real Time Clock (RTC)
DS1306EN	MAXI	N/a	105	avai	Serial Alarm Real Time Clock (RTC)
DS1306N	DALLAS	N/a	338	avai	Serial Alarm Real Time Clock (RTC)
DS1306N		N/a	2	avai	Serial Alarm Real Time Clock (RTC)