DS1306 Fast Delivery |IC PHOENIX CO.,LIMITED

DS1306 ,Serial Alarm Real Time Clock (RTC)PIN DESCRIPTIONV - Primary Power SupplyCC1V - Backup Power SupplyCC2V - +3V Battery InputBATV - Int ..
DS1306+ ,Serial Alarm Real-Time Clockblock diagram in Figure 1 shows the main elements of the serial alarm RTC. The followingparagraphs ..
DS1306E+ ,Serial Alarm Real-Time ClockPIN DESCRIPTIONV - Primary Power SupplyCC1V - Backup Power SupplyCC2V - +3V Battery InputBATV - Int ..
DS1306EN ,Serial Alarm Real Time Clock (RTC)block diagram in Figure 1 shows the main elements of the Serial Alarm RTC. The followingparagraphs ..
DS1306EN ,Serial Alarm Real Time Clock (RTC)PIN DESCRIPTIONV – Primary Power SupplyCC1ORDERING INFORMATIONV – Backup Power SupplyCC2DS1306 16-P ..
DS1306EN+ ,Serial Alarm Real-Time ClockFEATURES PIN ASSIGNMENT Real-time clock (RTC) counts seconds,1 20V VCC2 CC1minutes, hours, date of ..
DTC123EE ,Bias Resistor TransistorELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)ACharacteristic Symbol Min ..
DTC123EET1 ,Bias Resistor TransistorFeatures(OUTPUT)PIN 1R1• Simplifies Circuit DesignBASE(INPUT)• Reduces Board SpaceR2• Reduces Compo ..
DTC123EET1 ,Bias Resistor TransistorMAXIMUM RATINGS (T = 25°C unless otherwise noted)ASC−75/SOT−416CASE 463xx MRating Symbol Value Un ..
DTC123J ,Bias Resistor TransistorMaximum ratings are those values beyond which device damage can occur.See specific marking informat ..
DTC123JCA ,Conductor Holdings Limited - Digital Transistor
DTC123JE ,Bias Resistor TransistorFeatures(OUTPUT)PIN 1R1• Simplifies Circuit DesignBASE(INPUT)• Reduces Board SpaceR2• Reduces Compo ..

DS1306
Serial Alarm Real Time Clock (RTC)
FEATURESReal-time clock (RTC) counts seconds,
minutes, hours, date of the month, month,
day of the week, and year with leap-yearcompensation valid up to 210096-byte, battery-backed NV RAM for data
storageTwo time-of-day alarms, programmable on
combination of seconds, minutes, hours, andday of the week1Hz and 32.768kHz clock outputsSerial interface supports Motorola SPI™
(serial peripheral interface) serial data ports
or standard 3-wire interfaceBurst mode for reading/writing successive
addresses in clock/RAMDual-power supply pins for primary and
backup power suppliesOptional trickle charge output to backupsupply2.0V to 5.5V operationOptional industrial temperature range:
-40°C to +85°CAvailable in space-efficient, 20-pin TSSOPpackageUnderwriters Laboratory (UL) recognized
ORDERING INFORMATION
DS1306 16-Pin DIP (300mil)
DS1306N 16-Pin DIP (Industrial)DS1306E 20-Pin TSSOP (4.4mm)
DS1306EN 20-Pin TSSOP (Industrial)
PIN ASSIGNMENT
Package Dimension Information
http:///TechSupport/DallasPackInfo.htm
VCC2
VBAT
INT0
INT1
1Hz
GND
VCC1
32kHz
VCCIF
SDO
SDI
SCLK
SERMODE
VCC2
DS1306 16-Pin DIP (300mil)
INT0
1Hz
GND
VCC1
SDO
SDI
SCLK
SERMODE
VBAT
INT1
32kHz
VCCIF
DS1306
Serial Alarm Real-Time Clock
DS1306
PIN DESCRIPTION
VCC1 - Primary Power Supply
VCC2 - Backup Power Supply
VBAT - +3V Battery InputVCCIF - Interface Logic Power-Supply Input
GND - Ground
X1, X2 - 32.768kHz Crystal Connection
INT0 - Interrupt 0 Output
INT1 - Interrupt 1 Output
SDI - Serial Data In
SDO - Serial Data OutCE - Chip Enable
SCLK - Serial Clock
SERMODE - Serial Interface Mode
1Hz - 1Hz Output
32kHz - 32.768kHz Output
DESCRIPTION
The DS1306 serial alarm real-time clock (RTC) provides a full binary coded decimal (BCD) clock
calendar that is accessed by a simple serial interface. The clock/calendar provides seconds, minutes,
hours, day, date, month, and year information. The end of the month date is automatically adjusted for
months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. In addition, 96 bytes of NV RAM are provided for data
storage.
An interface logic-power supply input pin (VCCIF) allows the DS1306 to drive SDO and 32kHz pins to a
level that is compatible with the interface logic. This allows an easy interface to 3V logic in mixed supplysystems. The DS1306 offers dual-power supplies as well as a battery-input pin. The dual-power supplies
support a programmable trickle charge circuit that allows a rechargeable energy source (such as a super
cap or rechargeable battery) to be used for a backup supply. The VBAT pin allows the device to be backed
up by a non-rechargeable battery. The DS1306 is fully operational from 2.0V to 5.5V.
Two programmable time-of-day alarms are provided by the DS1306. Each alarm can generate an
interrupt on a programmable combination of seconds, minutes, hours, and day. “Don’t care” states can be
inserted into one or more fields if it is desired for them to be ignored for the alarm condition. A 1Hz and a
32kHz clock output are also available.
The DS1306 supports a direct interface to SPI serial data ports or standard 3-wire interface. An easy-to-
use address and data format is implemented in which data transfers can occur 1 byte at a time or in
multiple-byte burst mode.
DS1306
OPERATION
The block diagram in Figure 1 shows the main elements of the serial alarm RTC. The following
paragraphs describe the function of each pin.
Figure 1. BLOCK DIAGRAM
SIGNAL DESCRIPTIONS
VCC1 – DC power is provided to the device on this pin. VCC1 is the primary power supply.
VCC2 – This is the secondary power supply pin. In systems using the trickle charger, the rechargeable
energy source is connected to this pin.
VBAT – Battery input for any standard 3V lithium cell or other energy source. UL recognized to ensureagainst reverse charging current when used in conjunction with a lithium battery.
See “Conditions of Acceptability” at http:///TechSupport/QA/ntrl.htm.
VCCIF (Interface Logic Power Supply Input) – The VCCIF pin allows the DS1306 to drive SDO and32kHz output pins to a level that is compatible with the interface logic, thus allowing an easy interface to
3V logic in mixed supply systems. This pin is physically connected to the source connection of the p-
channel transistors in the output buffers of the SDO and 32kHz pins.
SERMODE (Serial Interface Mode Input) – The SERMODE pin offers the flexibility to choose
between two serial interface modes. When connected to GND, standard 3-wire communication is
selected. When connected to VCC, SPI communication is selected.
SCLK (Serial Clock Input) – SCLK is used to synchronize data movement on the serial interface for
either the SPI or 3-wire interface.
SDI (Serial Data Input) – When SPI communication is selected, the SDI pin is the serial data input forthe SPI bus. When 3-wire communication is selected, this pin must be tied to the SDO pin (the SDI and
DS1306
SDO (Serial Data Output) – When SPI communication is selected, the SDO pin is the serial data output
for the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDI pin (the SDI and
SDO pins function as a single I/O pin when tied together). VCCIF provides the logic high level.
CE (Chip Enable) – The chip enable signal must be asserted high during a read or a write for both 3-
wire and SPI communication. This pin has an internal 55k pulldown resistor (typical).
INT0 (Interrupt 0 Output) – The INT0 pin is an active-low output of the DS1306 that can be used as an
interrupt input to a processor. The INT0 pin can be programmed to be asserted by Alarm 0. The INT0 pin
remains low as long as the status bit causing the interrupt is present and the corresponding interrupt
enable bit is set. The INT0 pin operates when the DS1306 is powered by VCC1, VCC2, or VBAT. The INT0pin is an open-drain output and requires an external pullup resistor.
1Hz (1Hz Clock Output) – The 1Hz pin provides a 1Hz square wave output. This output is active when
the 1 Hz bit in the control register is a logic 1.
Both INT0 and 1Hz pins are open-drain outputs. The interrupt, 1Hz signal, and the internal clock continueto run regardless of the level of VCC (as long as a power source is present).
INT1 (Interrupt 1 Output) – The INT1 pin is an active high output of the DS1306 that can be used as an
interrupt input to a processor. The INT1 pin can be programmed to be asserted by Alarm 1. When an
alarm condition is present, the INT1 pin generates a 62.5ms active-high pulse. The INT1 pin operatesonly when the DS1306 is powered by VCC2 or VBAT. When active, the INT1 pin is internally pulled up to
VCC2 or VBAT. When inactive, the INT1 pin is internally pulled low.
32kHz (32.768kHz Clock Output) – The 32kHz pin provides a 32.768kHz output. This signal is always
present. VCCIF provides the logic high level.
X1, X2 – Connections for a standard 32.768kHz quartz crystal. The internal oscillator is designed for
operation with a crystal having a specified load capacitance of 6pF. For more information on crystalselection and crystal layout considerations, refer to Application Note 58, “Crystal Considerations with
Dallas Real-Time Clocks.” The DS1306 can also be driven by an external 32.768kHz oscillator. In this
configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
DS1306
CLOCK ACCURACYThe accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit can result in the clock running fast. Refer to Application
Note 58, “Crystal Considerations with Dallas Real-Time Clocks” for detailed information.
CLOCK, CALENDAR, AND ALARM
The time and calendar information is obtained by reading the appropriate register bytes. The RTC
registers are illustrated in Figure 2. The time, calendar, and alarm are set or initialized by writing the
appropriate register bytes. Note that some bits are set to 0. These bits always read 0 regardless of how
they are written. Also note that registers 12h to 1Fh (read) and registers 92h to 9Fh are reserved. These
registers always read 0 regardless of how they are written. The contents of the time, calendar, and alarmregisters are in the BCD format.
WRITING TO THE CLOCK REGISTERS
The internal time and date registers continue to increment during write operations. However, the
countdown chain is reset when the seconds register is written. Writing the time and date registers within
one second after writing the seconds register ensures consistent data.
Terminating a write before the last bit is sent aborts the write for that byte.
READING FROM THE CLOCK REGISTERS
Buffers are used to copy the time and date register at the beginning of a read. When reading in burst
mode, the user copy is static while the internal registers continue to increment.
DS1306
Figure 2. RTC REGISTERS AND ADDRESS MAP
Note: Range for alarm registers does not include mask’m’ bits.
The DS1306 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is
the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23hours).
The DS1306 contains two time-of-day alarms. Time-of-day alarm 0 can be set by writing to registers 87h
to 8Ah. Time-of-day Alarm 1 can be set by writing to registers 8 Bh to 8 Eh. Bit 7 of each of the time-of-
day alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, a time-of-day alarmonly occurs once per week when the values stored in timekeeping registers 00h to 03h match the values
stored in the time-of-day alarm registers. An alarm is generated every day when bit 7 of the day alarm
register is set to a logic 1. An alarm is generated every hour when bit 7 of the day and hour alarm
registers is set to a logic 1. Similarly, an alarm is generated every minute when bit 7 of the day, hour, and
minute alarm registers is set to a logic 1. When bit 7 of the day, hour, minute, and seconds alarm registers
DS1306
During each clock update, the RTC compares the Alarm 0 and Alarm 1 registers with the corresponding
clock registers. When a match occurs, the corresponding alarm flag bit in the status register is set to a 1. If
the corresponding alarm interrupt enable bit is enabled, an interrupt output is activated.
Table 1. TIME-OF-DAY ALARM MASK BITS
SPECIAL PURPOSE REGISTERS
The DS1306 has three additional registers (control register, status register, and trickle charger register)that control the real-time clock, interrupts, and trickle charger.
CONTROL REGISTER (READ 0FH, WRITE 8FH)
WP (Write Protect) – Before any write operation to the clock or RAM, this bit must be logic 0. When
high, the write protect bit prevents a write operation to any register, including bits 0, 1, and 2 of thecontrol register. Upon initial power-up, the state of the WP bit is undefined. Therefore, the WP bit should
be cleared before attempting to write to the device. When WP is set, it must be cleared before any other
control register bit can be written.
1Hz (1Hz Output Enable) – This bit controls the 1Hz output. When this bit is a logic 1, the 1Hz outputis enabled. When this bit is a logic 0, the 1Hz output is high-Z.
AIE0 (Alarm Interrupt Enable 0) – When set to a logic 1, this bit permits the interrupt 0 request flag
(IRQF0) bit in the status register to assert INT0. When the AIE0 bit is set to logic 0, the IRQF0 bit does
not initiate the INT0 signal.
AIE1 (Alarm Interrupt Enable 1) – When set to a logic 1, this bit permits the interrupt 1 request flag
(IRQF1) bit in the status register to assert INT1. When the AIE1 bit is set to logic 0, the IRQF1 bit does
not initiate an interrupt signal, and the INT1 pin is set to a logic 0 state.
STATUS REGISTER (READ 10H)
IRQF0 (Interrupt 0 Request Flag) – A logic 1 in the interrupt request flag bit indicates that the current
time has matched the Alarm 0 registers. If the AIE0 bit is also a logic 1, the INT0 pin goes low. IRQF0 is
cleared when the address pointer goes to any of the Alarm 0 registers during a read or write. IRQF0 isactivated when the device is powered by VCC1, VCC2, or VBAT.
DS1306
active-high pulse. IRQF1 is cleared when the address pointer goes to any of the alarm 1 registers during a
read or write. IRQF1 is activated only when the device is powered by VCC2 or VBAT.
TRICKLE CHARGE REGISTER (READ 11H, WRITE 91H)
This register controls the trickle charge characteristics of the DS1306. The simplified schematic of Figure
3 shows the basic components of the trickle charger. The trickle charge select (TCS) bits (bits 4–7)control the selection of the trickle charger. In order to prevent accidental enabling, only a pattern of 1010
enables the trickle charger. All other patterns disable the trickle charger. The DS1306 powers up with the
trickle charger disabled. The diode select (DS) bits (bits 2–3) select whether one diode or two diodes are
connected between VCC1 and VCC2. The diode select (DS) bits (bits 2–3) select whether one diode or two
diodes are connected between VCC1 and VCC2. The resistor select (RS) bits select the resistor that isconnected between VCC1 and VCC2. The resistor and diodes are selected by the RS and DS bits as shown
in Table 2.
Figure 3. PROGRAMMABLE TRICKLE CHARGER
DS1306
Table 2. TRICKLE CHARGER RESISTOR AND DIODE SELECT
If RS is 00, the trickle charger is disabled independently of TCS.
Diode and resistor selection is determined by the user according to the maximum current desired forbattery or super cap charging. The maximum charging current can be calculated as illustrated in the
following example. Assume that a system power supply of 5V is applied to VCC1 and a super cap is
connected to VCC2. Also assume that the trickle charger has been enabled with one diode and resister R1
between VCC1 and VCC2. The maximum current IMAX would, therefore, be calculated as follows:
IMAX = (5.0V - diode drop) / R1 � (5.0V - 0.7V) / 2kΩ � 2.2mA
As the super cap charges, the voltage drop between VCC1 and VCC2 decreases and, therefore, the charge
current decreases.
POWER CONTROL
Power is provided through the VCC1, VCC2, and VBAT pins. Three different power supply configurations
are illustrated in Figure 4. Configuration 1 shows the DS1306 being backed up by a non-rechargeable
energy source such as a lithium battery. In this configuration, the system power supply is connected to
VCC1 and VCC2 is grounded. When VCC falls below VBAT the device switches into a low-current battery
backup mode. Upon power-up, the device switches from VBAT to VCC when VCC is greater thanVBAT + 0.2V. The device is write-protected whenever it is switched to VBAT.
Configuration 2 illustrates the DS1306 being backed up by a rechargeable energy source. In this case, the
VBAT pin is grounded, VCC1 is connected to the primary power supply, and VCC2 is connected to the
secondary supply (the rechargeable energy source). The DS1306 operates from the larger of VCC1 orVCC2. When VCC1 is greater than VCC2 + 0.2V (typical), VCC1 powers the DS1306. When VCC1 is less than
VCC2, VCC2 powers the DS1306. The DS1306 does not write-protect itself in this configuration.
Configuration 3 shows the DS1306 in battery-operate mode, where the device is powered only by a single
battery. In this case, the VCC1 and VBAT pins are grounded and the battery is connected to the VCC2 pin.
Only these three configurations are allowed. Unused supply pins must be grounded.
DS1306
Figure 4. POWER SUPPLY CONFIGURATIONS
Configuration 1: Backup Supply is a Nonrechargeable Lithium Battery
Configuration 2: Backup Supply is a Rechargeable Battery or Super Capacitor

Configuration 3: Battery Operate Mode

Note: Device does not provide automatic write protection.
Note: Device is write-protected if VCC < VCCTP.
DS1306
SERIAL INTERFACE
The DS1306 offers the flexibility to choose between two serial interface modes. The DS1306 can
communicate with the SPI interface or with a standard 3-wire interface. The interface method used is
determined by the SERMODE pin. When this pin is connected to VCC, SPI communication is selected.
When this pin is connected to ground, standard 3-wire communication is selected.
SERIAL PERIPHERAL INTERFACE (SPI)
The serial peripheral interface (SPI) is a synchronous bus for address and data transfer and is used wheninterfacing with the SPI bus on specific Motorola microcontrollers such as the 68HC05C4 and the
68HC11A8. The SPI mode of serial communication is selected by tying the SERMODE pin to VCC.
Four pins are used for the SPI. The four pins are the SDO (serial data out), SDI (serial data in), CE (chip
enable), and SCLK (serial clock). The DS1306 is the slave device in an SPI application, with themicrocontroller being the master.
The SDI and SDO pins are the serial data input and output pins for the DS1306, respectively. The CE
input is used to initiate and terminate a data transfer. The SCLK pin is used to synchronize datamovement between the master (microcontroller) and the slave (DS1306) devices.
The shift clock (SCLK), which is generated by the microcontroller, is active only during address and data
transfer to any device on the SPI bus. The inactive clock polarity is programmable in some
microcontrollers. The DS1306 determines on the clock polarity by sampling SCLK when CE becomesactive. Therefore either SCLK polarity can be accommodated. Input data (SDI) is latched on the internal
strobe edge and output data (SDO) is shifted out on the shift edge (Figure 5). There is one clock for each
bit transferred. Address and data bits are transferred in groups of eight.

Partno	Mfg	Dc	Qty	Available	Descript
DS1306		N/a	3	avai	Serial Alarm Real Time Clock (RTC)