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DS12C887ADALLASN/a33avaiReal-Time Clock


DS12C887A ,Real-Time ClockPIN DESCRIPTION Daylight Savings Time optionAD0–AD7 - Multiplexed Address/Data Bus Selectable bet ..
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DS12C887A
Real-Time Clock
FEATURESDrop-in replacement for IBM AT computer
clock/calendarPin compatible with the MC146818B and
DS1287ATotally nonvolatile with over 10 years of
operation in the absence of powerSelf-contained subsystem includes lithium,
quartz, and support circuitryCounts seconds, minutes, hours, days, day ofthe week, date, month, and year with leap-
year compensation valid up to 2100Binary or BCD representation of time,
calendar, and alarm12- or 24-hour clock with AM and PM in 12-hour modeDaylight Savings Time optionSelectable between Motorola and Intel bus
timingMultiplex bus for pin efficiencyInterfaced with software as 128 RAM
locations
– 15 bytes of clock and control registers
– 113 bytes of general purpose RAMProgrammable square-wave output signalBus-compatible interrupt signals (IRQ)Three interrupts are separately software-
maskable and testable
– Time-of-day alarm once/second to
once/day
– Periodic rates from 122�s to 500ms
– En-of-clock update cycleCentury register
PIN ASSIGNMENT
PIN DESCRIPTION
AD0–AD7-Multiplexed Address/Data Bus-No Connect
MOT-Bus Type Selection-RTC Chip Select Input-Address StrobeW-Read/Write Input-Data Strobe
RESET-Reset Input
IRQ-Interrupt Request Output
SQW-Square-Wave Output
VCC-+5V Main Supply
RCLR-RAM Clear
GND-Ground
DESCRIPTION

The DS12C887A real-time clock plus RAM is designed to be a direct upgrade replacement for the
DS12887A in existing IBM-compatible personal computers to add hardware year-2000 compliance. A
century byte was added to memory location 50, 32h, as called out by the PC AT specification. The
DS12C887A is identical in form, fit, and function to the DS1287A, and provides additional 64 bytes of
general-purpose RAM. Access to this additional RAM space is determined by the logic level presented on
Real-Time Clock

MOT
DS12C887A
24-Pin Encapsulated Package
AD1
AD3
AD4
AD5
AD6
AD7
GND
VCC
SQW
IRQ
RESET
R/W
AD0
AD2
RCLR
DS12C887A
to clear the RAM, RCLR must be forced to an input logic 0 (-0.3V to +0.8V) during battery-backup mode
when VCC is not applied. The RCLR function is designed to be used via human interface (shorting to
ground manually or by switch) and not to be driven with external buffers.
For a complete description of operating conditions, electrical characteristics, bus timing and pin
descriptions other than RCLR, see the DS12C887 data sheet.
DS12C887 REAL-TIME CLOCK PLUS RAM

Note:
Pins 2, 3, 16, 20, and 22 are missing by design.
This device cannot be stored or shipped in conductive
material that will give a continuity path between the RAM
clear pin and ground.
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