DS1270AB-100# ,16M Nonvolatile SRAMFEATURES PIN ASSIGNMENT 5 years minimum data retention in the NC 1 36 V CCabsence of external ..
DS1270AB-100IND ,16M Nonvolatile SRAMFEATURES PIN ASSIGNMENT 5 years minimum data retention in the NC 1 36 V CCabsence of external ..
DS1270AB-70 ,16M Nonvolatile SRAM DS1270Y/AB 16M Nonvolatile SRAM
DS1270AB-70# ,16M Nonvolatile SRAM19-5615; Rev 11/10 DS1270Y/AB 16M Nonvolatile SRAM
DS1270AB-70IND ,16M Nonvolatile SRAMFEATURES PIN ASSIGNMENT 5 years minimum data retention in the NC 1 36 V CCabsence of external ..
DS1270W-100IND ,3.3V 16Mb Nonvolatile SRAMPIN DESCRIPTION A0–A20 - Address Inputs DQ0–DQ7 - Data In/Data Out CE - Chip Enable WE - Wri ..
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DS1270AB-100#-DS1270AB-70#
16M Nonvolatile SRAM
FEATURES 5 years minimum data retention in the
absence of external power Data is automatically protected during power
loss Unlimited write cycles Low-power CMOS operation Read and write access times of 70 ns Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time Full ±10% VCC operating range (DS1270Y) Optional ±5% VCC operating range
(DS1270AB) Optional industrial temperature range of
-40°C to +85°C, designated IND
PIN ASSIGNMENT
PIN DESCRIPTION A0 – A20 - Address Inputs
DQ0 - DQ7 - Data In/Data Out - Chip Enable - Write Enable - Output Enable
VCC - Power (+5V)
GND - Ground
NC - No Connect
DESCRIPTION The DS1270 16M Nonvolatile SRAMs are 16,777,216-bit, fully static nonvolatile SRAMs organized as
2,097,152 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. There is no limit on the number of write cycles which can be executed and no
additional support circuitry is required for microprocessor interfacing.
DS1270Y/AB
16M Nonvolatile SRAM
13
10
11
12
14
35
36-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED A18A14
A7
A6
A5
A4
A3
A2
A0
A1
VCC
A19
NC
A15
A17
WE
A13
A8
A9
A11
OE
A10
DQ7
CE
36
34
33
32
31
30
29
28
27
26
25
23
24 A20
A16
A12
NC
DQ0
DQ1
15
16
22
21
DQ6
DQ5
17
18 GND
DQ2
DQ3
DQ4
19
20
19-5615; Rev 11/10
DS1270Y/AB
READ MODE The DS1270 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 21 address inputs
(A0 - A20) defines which of the 2,097,152 bytes of data is accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE) and the limiting
parameter is either tCO for CE or tOE for OE rather than tACC.
WRITE MODE The DS1270 devices execute a write cycle whenever WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE
will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE The DS1270AB provides full-functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1270Y provides full-functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become don’t care, and all outputs become high-
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1270AB and 4.5 volts for the
DS1270Y.
FRESHNESS SEAL Each DS1270 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is
enabled for battery backup operation.
DS1270Y/AB
ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Storage Temperature -40°C to +85°C
Lead Temperature (soldering, 10s) +260°C
Note: EDIP is wave or hand soldered only.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES DS1270AB Power Supply Voltage VCC 4.75 5.0 5.25 V
DS1270Y Power Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 Input Voltage VIH 2.2 VCC V
Logic 0 Input Voltage VIL 0 +0.8 V
DC ELECTRICAL (VCC=5V ± 5% for DS1270AB)
CHARACTERISTICS (TA: See Note 10) (VCC=5V ± 10% for DS1270Y)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current IIL -4.0 +4.0 µA
I/O Leakage Current IIO -4.0 +4.0 µA
Output Current @ 2.4V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
Standby Current CE=2.2V ICCS1 1.0 1.5 mA
Standby Current CE=VCC-0.5V ICCS2 100 250 µA
Operating Current ICCO1 85 mA
Write Protection Voltage (DS1270AB) VTP 4.50 4.62 4.75 V
Write Protection Voltage (DS1270Y) VTP 4.25 4.37 4.5 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance CIN 20 40 pF
Output Capacitance CI/O 20 40 pF
DS1270Y/AB
AC ELECTRICAL (VCC=5V ± 5% for DS1270AB)
CHARACTERISTICS (TA: See Note 10) (VCC=5V ± 10% for DS1270Y)
PARAMETER SYMBOL
DS1270AB-70
DS1270Y-70 UNITS NOTES
MIN MAX Read Cycle Time tRC 70 ns
Access Time tACC 70 ns to Output Valid tOE 35 ns to Output Valid tCO 70 ns or CE to Output Active tCOE 5 ns 5
Output High Z from Deselection tOD 25 ns 5
Output Hold from Address Change tOH 5 ns
Write Cycle Time tWC 70 ns
Write Pulse Width tWP 55 ns 3
Address Setup Time tAW 0 ns
Write Recovery Time tWR1
tWR2
15 ns
ns
12
13
Output High Z from WE tODW 25 ns 5
Output Active from WE tOEW 5 ns 5
Data Setup Time tDS 30 ns 4
Data Hold Time tDH1
tDH2
10 ns
ns
12
13
TIMING DIAGRAM: READ CYCLE
SEE NOTE 1
DS1270Y/AB
TIMING DIAGRAM: WRITE CYCLE 1
TIMING DIAGRAM: WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
DS1270Y/AB
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to CE and WE Inactive tPD 1.5 µs 11
VCC slew from VTP to 0V tF 150 µs
VCC slew from 0V to VTP tR 150 µs
VCC Valid to CE and WE Inactive tPU 2 ms
VCC Valid to End of Write Protection tREC 125 ms
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention Time tDR 5 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
