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DS1254WB2-150-DS1254YB2-100
2M x 8 NV SRAM with Phantom Clock
GENERAL DESCRIPTION The DS1254 is a fully nonvolatile static RAM (NV SRAM)
(organized as 2M words by 8 bits) with built-in real-time
clock. It has a self-contained lithium energy source and
control circuitry that constantly monitors VCC for an out-of-
tolerance condition. When such a condition occurs, the
DS1254 makes use of an attached DS3800 battery cap to
maintain clock information and preserve stored data while
protecting that data by disallowing all memory accesses.
Additionally, the DS1254 has dedicated circuitry for
monitoring the status of an attached DS3800 battery cap.
FEATURES Real-Time Clock (RTC) Keeps Track of Hundredths of
Seconds, Seconds, Minutes, Hours, Days, Date,
Months, and Years with Automatic Leap-Year
Compensation Valid Up to the Year 2100 2M x 8 NV SRAM Watch Function is Transparent to RAM Operation Automatic Data Protection During Power Loss Unlimited Write-Cycle Endurance Surface-Mountable BGA Module Construction Over 10 Years of Data Retention in the Absence of
Power Battery Monitor Checks Remaining Capacity Daily +3.3V Operation Underwriters Laboratory (UL) Recognized
(/qa/info/ul/)
APPLICATIONS Telecom Switches
Routers
RAID Systems
PACKAGE OUTLINE
TYPICAL OPERATING CIRCUIT
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE VOLTAGE RANGE
(V) TOP MARK DS1254WB-150 0°C to +70°C 40mm BGA 3.3 DS1254W-150
DS1254WB2-150 0°C to +70°C 40mm BGA 3.3 DS1254W-150
DS1254
2M x 8 NV SRAM with Phantom Clock
Side -A- Shown
(For Reference Only, Not to Scale)
Component placement may vary.
19-4621; 12/09
+3.3V
DS1254
DETAILED DESCRIPTION The DS1254 is a fully nonvolatile static RAM (NV SRAM) (organized as 2M words by 8 bits) with built-in real-time
clock. It has a self-contained lithium energy source and control circuitry that constantly monitors VCC for an out-of-
tolerance condition. When such a condition occurs, the DS1254 makes use of an attached DS3800 battery cap to
maintain clock information and preserve stored data while protecting that data by disallowing all memory accesses.
Additionally, the DS1254 has dedicated circuitry for monitoring the status of an attached DS3800 battery cap.
The phantom clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours,
day, date, month, and year information. The date at the end of the month is automatically adjusted for months with
fewer than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or 12-hour
format with an AM/PM indicator.
Because the DS1254 has a total of 168 balls and only 35 active signals, balls are wired together into groups, thus
providing redundant connections for every signal.
Figure 1. Pin Configuration VCC
A7
A6
A5
GND
A4
A3
A2
A1 10 11 12 13 14 15 16 17 18 19 20 4039383736353433323130
VCC
A17
A18
A19
GND
A20
CE
OE
WE
DQ0DQ1DQ2DQ3
GND
DQ4DQ5DQ6DQ7
CC A8 A9 A10 A11GND A12 A13 A14 A15 A16 V
RECEPTACLES FOR
DS3800 BATTERY CAP
PINS
GND
VBAT
Dallas Semiconductor
DS1254
DS1254
RAM READ MODE The DS1254 executes a read cycle whenever WE is inactive (high) and CE is active (low). The unique address
specified by the 21 address inputs (A0–A20) defines which of the 2MB of data is to be accessed. Valid data will be
available to the eight data-output drivers within tACC (access time) after the last address input is stable, providing
that CE and OE access times and states are also satisfied. If OE and CE access times are not satisfied, then data
access must be measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for CE
or tOE for OE rather than address access.
RAM WRITE MODE The DS1254 is in the write mode whenever WE and CE are in their active (low) state after address inputs are
stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is
terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle.
WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE
control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus
has been enabled (CE and OE active), then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE The device is fully accessible and data can be written and read only when VCC is greater than VPF. However, when CC falls below the power-fail point, VPF (point at which write protection occurs), the internal clock registers and
SRAM are blocked from any access. When VCC falls below VBAT, device power is switched from the VCC to VBAT.
RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. All signals
must be powered down when VCC is powered down.
PHANTOM CLOCK OPERATION Communication with the phantom clock is established by pattern recognition on a serial bit stream of 64 bits that
must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. All accesses that
occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the phantom clock,
and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip
enable (CE), output enable (OE), and write enable (WE). Initially, a read cycle to any memory location using the CE
and OE control of the phantom clock starts the pattern-recognition sequence by moving a pointer to the first bit of
the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CE and WE signals of the
device. These 64 write cycles are used only to gain access to the phantom clock. Therefore, any address within the
first 512kB of memory, (00h to 7FFFFh) is acceptable. However, the write cycles generated to gain access to the
phantom clock are also writing data to a location in the memory. The preferred way to manage this requirement is
to set aside just one address location in memory as a phantom clock scratch pad. When the first write cycle is
executed, it is compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the
next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does
not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern
recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition
continues for a total of 64 write cycles as described above until all the bits in the comparison register have been
DS1254
data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to
either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other
locations outside the memory block can be interleaved with CE cycles without interrupting the pattern-recognition
sequence or data-transfer sequence to the phantom clock.
PHANTOM CLOCK REGISTER INFORMATION The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially accessed one
bit at a time after the 64-bit pattern-recognition sequence has been completed. When updating the phantom clock
registers, each register must be handled in groups of 8 bits. Writing and reading individual bits within a register
could produce erroneous results. These read/write registers are defined in Figure 3.
Figure 2. Phantom Clock Protocol Definition
NOTE: THE PATTERN RECOGNITION IN HEX IS C5, 3A, A3, 5C, C5, 3A, A3, 5C. THE ODDS OF THIS PATTERN BEING ACCIDENTALLY DUPLICATED AND CAUSING INADVERTENT ENTRY TO THE PHANTOM CLOCK IS LESS THAN 1 IN 1019. THIS PATTERN IS SENT TO THE PHANTOM CLOCK LSB TO MSB.
DS1254
Figure 3. Phantom Clock Register Definition DS1254
AM/PM/12/24 MODE Bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. When high, the 12-hour mode is
selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the
second 10-hour bit (20–23 hours).
OSCILLATOR BIT Bit 5 of the day register controls the oscillator. When set to logic 1, the oscillator is off. When set to logic 0, the
oscillator turns on and the watch becomes operational.
ZERO BITS Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that will always read logic 0. When writing these locations,
either a logic 1 or logic 0 is acceptable.
BATTERY MONITORING The DS1254 automatically monitors the battery in an attached DS3800 battery cap on a 24-hour time interval. Such
monitoring begins within tREC after VCC rises above VPF and is suspended when power failure occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1M test resistor for one second.
During this one second, if the battery voltage falls below the battery-voltage trip point (~2.6V), the battery warning
output BW is asserted. Once asserted, BW remains active until the attached DS3800 battery cap is replaced.
However, the battery is still retested after each VCC power-up, even if it was active on power-down. If the battery
voltage is found to be higher than ~2.6V during such testing, BW is de-asserted and regular testing resumes. BW
has an open-drain output driver.
DS1254
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground -0.3V to +4.6V
Operating Temperature Range 0C to +70C
Storage Temperature Range -40C to +70C
Soldering Temperature See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
RECOMMENDED DC OPERATING CONDITIONS (TA = 0C to +70C)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Power-Supply Voltage VCC 3.0 3.3 3.7 V 1
Logic 1 Voltage (All Inputs) VIH 2.0 VCC +
0.3 V 1
Logic 0 Voltage (All Inputs) VIL -0.3 0.6 V 1
DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V 10%, TA = 0C to +70C.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current IIL -4.0 +4.0 A
I/O Leakage Current IIO -4.0 +4.0 A
Output Current at 2.4V IOH -1.0 mA 3
Output Current at 0.4V IOL 2.0 mA 3
Standby Current (CE = 2.2V) ICCS1 5.0 7 mA
Standby Current (CE = VCC - 0.5V) ICCS2 2.0 3.0 mA
Operating Current, tCYC = 100ns ICCO1 50 mA
Write Protection Voltage VPF 2.8 2.97 V 1
CAPACITANCE (TA = +25C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance: A0 to A18, OE,
WE, CE CIN 25 50 pF
Input Capacitance: A19 to A20 CIN 5 10 pF
I/O Capacitance: DQ0 to DQ7 CIO 25 50 pF
Output Capacitance: BW COUT 5 10 pF
DS1254
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V 10%, TA = 0C to +70C.)
PARAMETER SYMBOL MIN MAX UNITS NOTES
Read Cycle Time tRC 150 ns
Address Access Time tAAC 150 ns
OE to Output Valid tOE 75 ns
CE to Output Valid tCO 150 ns
CE or OE to Output Active tCOE 0 ns 2
Output High-Z from Deselection tOD 70 ns 2
Output Hold from Address Change tOH 5 ns
Write Cycle Time tWC 150 ns
WE, CE Pulse Width tWP 100 ns 5
Address Setup Time tAW 10 ns
tAH1 5 ns 6 Address Hold Time tAH2 25 ns 7
Output High-Z from WE tODW 70 ns 2
Output Active from WE tOEW 5 ns 2
Data Setup Time tDS 60 ns 8
tDH1 0 ns 6 Data Hold Time tDH2 20 ns 8
Read Recovery (Clock Access Only) tRR 20 ns
Write Recovery (Clock Access Only) tWR 20 ns
POWER-UP/POWER-DOWN CHARACTERISTICS
(VCC = 3.3V 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE and WE at VIH Before Power-Down tPD 0 s
VCC Fall Time: VPF(MAX) to VPF(MIN) tF 300 s
VCC Fall Time: VPF(MIN) to VBAT tFB 10 s
VCC Rise Time: 0V to VPF(MIN) tR 150 s
VCC Valid to End of Write Protection tREC 125 ms
VCC Valid to BW Valid tBPU 1 s 3
(TA = +25C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data-Retention Time (Oscillator On) tDR 10 years 4
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when
device is in battery-backup mode.
DS1254
BATTERY WARNING TIMING
(VCC = 3.3V 10%, TA = 0C to +70C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Battery Test Cycle tBTC 24 hour
Battery Test Pulse Width tBTPW 1 seconds
Battery Test to BW Active tBW 1 seconds
VCC Valid to BW Valid tBPU 1 seconds 3
AC TEST CONDITIONS
Output Load: 100pF + 1 TTL Gate
Input Pulse Levels: 0V to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
Figure 4. Memory Read Cycle Timing (Note 9)
tRC
ADDRESS
tACC
CE
OE
DQ0–DQ7
tOH
tCO
tOE
tCOEtCOE
tOD
tOD
OUTPUT
DATA VALID
