DS1250WP-150 ,3.3V 4096K Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theA18 32 V1 CCabsence of external powe ..
DS1250WP-150 ,3.3V 4096K Nonvolatile SRAMPIN DESCRIPTIONA0 - A18 - Address InputsDQ0 - DQ7 - Data In/Data OutCE - Chip EnableWE - Write Enab ..
DS1250Y ,4096k Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in the A18 1 32 V CCabsence of extern ..
DS1250Y/70IND+ ,4096k Nonvolatile SRAM 19-5647; Rev 12/10 DS1250Y/AB 4096k Nonvolatile SRAM
DS1250Y-100 ,4096K Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theA18 32 V1 CCabsence of external powe ..
DS1250Y-100+ ,4096k Nonvolatile SRAM 19-5647; Rev 12/10 DS1250Y/AB 4096k Nonvolatile SRAM
DTC024EUB , 100mA/50V Digital transistors(with built-in resistors)
DTC113ZUA , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DTC113ZUA , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DTC113ZUA , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DTC113ZUA , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DTC114 , NPN Small Signal Transistor Small Signal Diode
DS1250WP-150
3.3V 4096k Nonvolatile SRAM
FEATURES10 years minimum data retention in the
absence of external powerData is automatically protected during powerlossReplaces 512k x 8 volatile static RAM,
EEPROM or Flash memoryUnlimited write cyclesLow-power CMOSRead and write access times as fast as 150 nsLithium energy source is electrically
disconnected to retain freshness until power is
applied for the first timeOptional industrial temperature range of
-40°C to +85°C, designated INDJEDEC standard 32-pin DIP packageNew PowerCap Module (PCM) packageDirectly surface-mountable module- Replaceable snap-on PowerCap provides
lithium backup batteryStandardized pinout for all nonvolatile
SRAM productsDetachment feature on PCM allows easyremoval using a regular screwdriver
PIN ASSIGNMENT
PIN DESCRIPTIONA0 - A18 - Address Inputs
DQ0 - DQ7 - Data In/Data Out - Chip Enable - Write Enable - Output Enable
VCC - Power (+3.3V)GND - Ground
DS1250W
3.3V 4096k Nonvolatile SRAM32-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
A14
DQ1
DQ0
VCC
DQ7
DQ5
DQ6
A16
A12
A18
DQ2
GND
DQ4
DQ3NCA15A16NCVCC
WEOECEDQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0GND
34-PIN POWERCAP MODULE (PCM)
(USES DS9034PC POWERCAP)
DS1250W
DESCRIPTIONThe DS1250W 3.3V 4096k Nonvolatile SRAM is a 4,194,304-bit, fully static, nonvolatile SRAM
organized as 524,288 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1250W devices can be used in place of existing 512kx 8 static RAMs directly conforming to the popular bytewide 32-pin DIP standard. DS1250W devices in
the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODEThe DS1250W executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs
(A0 - A18) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to theeight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODEThe DS1250W executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE
will disable the outputs in tODW from its falling edge.
DATA RETENTION MODEThe DS1250W provides full functional capability for VCC greater than 3.0 volts and write protects by 2.8volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile
static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As VCC
falls below approximately 2.5 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when VCC rises above approximately 2.5 volts, the powerswitching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal
RAM operation can resume after VCC exceeds 3.0 volts.
FRESHNESS SEALEach DS1250W device is shipped from Dallas Semiconductor with its lithium energy source
disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than 3.0
volts, the lithium energy source is enabled for battery back-up operation.
PACKAGESThe DS1250W is available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-
DS1250W
memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1250W PCM
device to be surface mounted without subjecting its lithium backup battery to destructive high-
temperature reflow soldering. After a DS1250W module base is reflow soldered, a DS9034PC PowerCapis snapped on top of the base to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to
prevent improper attachment. DS1250W module bases and DS9034PC PowerCaps are ordered separately
and shipped in separate containers. See the DS9034PC data sheet for further information.
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -0.3V to +4.6V
Operating Temperature 0°C to 70°C, -40°C to +85°C for IND parts
Storage Temperature -40°C to +70°C, -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 secondsThis is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
DC ELECTRICAL CHARACTERISTICS (tA: See Note 10) (VCC=3.3V ±=0.3V)
CAPACITANCE (tA=25°C)
DS1250W
AC ELECTRICAL CHARACTERISTICS (tA: See Note 10) (VCC=3.3V ±=0.3V)
READ CYCLESEE NOTE 1
DS1250W
WRITE CYCLE 1SEE NOTES 2, 3, 4, 6, 7, 8, AND 12
DS1250W
WRITE CYCLE 2SEE NOTES 2, 3, 4, 6, 7, 8, AND 12
POWER-DOWN/POWER-UP CONDITION
