DS1250Y/70IND+ ,4096k Nonvolatile SRAM 19-5647; Rev 12/10 DS1250Y/AB 4096k Nonvolatile SRAM
DS1250Y-100 ,4096K Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theA18 32 V1 CCabsence of external powe ..
DS1250Y-100+ ,4096k Nonvolatile SRAM 19-5647; Rev 12/10 DS1250Y/AB 4096k Nonvolatile SRAM
DS1250Y-100IND+ ,4096k Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in the A18 1 32 V CCabsence of extern ..
DS1250Y-70 ,4096K Nonvolatile SRAMDS1250Y/AB4096k Nonvolatile SRAMwww.dalsemi.com
DS1250Y-70 ,4096K Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theA18 32 V1 CCabsence of external powe ..
DTC113ZUA , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DTC113ZUA , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
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DTC114 , NPN Small Signal Transistor Small Signal Diode
DTC114E ,NPN SILICON BIAS RESISTOR TRANSISTORELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)ACharacteristic Symbol Min ..
DS1250AB-100+-DS1250AB-100IND+-DS1250AB-70+-DS1250AB-70IND+-DS1250ABP-100+-DS1250ABP-70-DS1250ABP-70+-DS1250ABP-70IND+-DS1250Y/70IND+-DS1250Y-100+-DS1250Y-100IND+-DS1250Y-70+-DS1250Y-70IND+-DS1250YP-100-DS1250YP-70-DS1250YP-70+-DS1250YP-70IND+
4096k Nonvolatile SRAM
FEATURES 10 years minimum data retention in the
absence of external power Data is automatically protected during power
loss Replaces 512k x 8 volatile static RAM,
EEPROM or Flash memory Unlimited write cycles Low-power CMOS Read and write access times of 70ns Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time Full ±10% VCC operating range (DS1250Y) Optional ±5% VCC operating range
(DS1250AB) Optional industrial temperature range of
-40°C to +85°C, designated IND JEDEC standard 32-pin DIP package PowerCap Module (PCM) package Directly surface-mountable module Replaceable snap-on PowerCap provides
lithium backup battery Standardized pinout for all nonvolatile
SRAM products Detachment feature on PCM allows easy
removal using a regular screwdriver
PIN ASSIGNMENT
PIN DESCRIPTION A0 - A18 - Address Inputs
DQ0 - DQ7 - Data In/Data Out - Chip Enable - Write Enable - Output Enable
VCC - Power (+5V)
GND - Ground
NC - No Connect
DS1250Y/AB
4096k Nonvolatile SRAM
13
10
11
12
14
31
32-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED A14A7 A5
A4
A3
A2
A1
A0
DQ1
DQ0
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20 A16
A12
A6
A18
DQ2
GND
15
16
18
17
DQ4
DQ3 NC 2 3 A15
A16
NC VCC
WE
OE CE DQ7
DQ6 DQ5
DQ4 DQ3
DQ2
DQ1 DQ0
GND 5 6 9
10
11 12
13 14
15
16 17
A17
A14
33 32 31
30
29 28 27
26
25 24
23
22 21
20 19
18
A13 A12 A11
A10
A9 A8
A7
A6 A5
A4 A3
A2
A1 A0
34 A18
GND VBAT
34-Pin POWERCAP MODULE (PCM)
(Uese DS9034PC+ or DS9034PCI+ POWERCAP)
19-5647; Rev 12/10
DS1250Y/AB
DESCRIPTION The DS1250 4096k Nonvolatile SRAMs are 4,194,304-bit, fully static, nonvolatile SRAMs organized as
524,288 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1250 devices can be used in place of existing 512k x
8 static RAMs directly conforming to the popular byte-wide 32-pin DIP standard. DS1250 devices in the
PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODE The DS1250 executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable)
and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs (A0 -
A18) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the eight
data output drivers within tACC (Access Time) after the last address input signal is stable, providing that and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied,
then data access must be measured from the later-occurring signal (CE or OE) and the limiting parameter
is either tCO for CE or tOE for OE rather than address access.
WRITE MODE The DS1250 executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE
will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE The DS1250AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1250Y provides full functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1250AB and 4.5 volts for the
DS1250Y.
FRESHNESS SEAL Each DS1250 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When VCC is first applied at a level greater than 4.25 volts, the lithium energy source
is enabled for battery back-up operation.
DS1250Y/AB
PACKAGES The DS1250 is available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-pin
DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1250 PCM
device to be surface mounted without subjecting its lithium backup battery to destructive high-
temperature reflow soldering. After a DS1250 PCM module base is reflow soldered, a DS9034PC
PowerCap is snapped on top of the PCM to form a complete Nonvolatile SRAM module. The DS9034PC
is keyed to prevent improper attachment. DS1250 module bases and DS9034PC PowerCaps are ordered
separately and shipped in separate containers. See the DS9034PC data sheet for further information.
DS1250Y/AB
ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Storage Temperature
EDIP -40°C to +85°C
PowerCap -55°C to +125°C
Lead Temperature (soldering, 10s) +260°C
Soldering Temperature (reflow, PowerCap) +260°C
Note: EDIP is wave or hand soldered only.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES DS1250AB Power Supply
Voltage
VCC 4.75 5.0 5.25 V
DS1250Y Power Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 +0.8 V
DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5% for DS1250AB) (TA: See Note 10) (VCC = 5V ±10% for DS1250Y)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current IIL -1.0 +1.0 µA
I/O Leakage Current CE ≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current @ 2.4V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
Standby Current CE=2.2V ICCS1 200 600 μA
Standby Current CE=VCC-0.5V ICCS2 50 150 μA
Operating Current ICCO1 85 mA
Write Protection Voltage (DS1250AB) VTP 4.50 4.62 4.75 V
Write Protection Voltage (DS1250Y) VTP 4.25 4.37 4.5 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance CIN 5 10 pF
Input/Output Capacitance CI/O 5 10 pF
DS1250Y/AB C ELECTRICAL CHARACTERISTICS (VCC = 5V ±5% for DS1250AB)
(TA: See Note 10) (VCC = 5V ±10% for DS1250Y)
PARAMETER SYMBOL
DS1250AB-70
DS1250Y-70 UNITS NOTES
MIN MAX Read Cycle Time tRC 70 ns
Access Time tACC 70 ns to Output Valid tOE 35 ns to Output Valid tCO 70 ns or CE to Output Active tCOE 5 ns 5
Output High-Z from Deselection tOD 25 ns 5
Output Hold from Address Change tOH 5 ns
Write Cycle Time tWC 70 ns
Write Pulse Width tWP 55 ns 3
Address Setup Time tAW 0 ns
Write Recovery Time tWR1
tWR2
5
15 ns
ns
12
13
Output High-Z from WE tODW 25 ns 5
Output Active from WE tOEW 5 ns 5
Data Setup Time tDS 30 ns 4
Data Hold Time tDH1
tDH2
0
10 ns
ns
12
13
DS1250Y/AB
READ CYCLE SEE NOTE 1
WRITE CYCLE 1 SEE NOTES 2, 3, 4, 6, 7, 8, and 12
