DS1244Y-70 ,256k NV SRAM with phantom clock, 70nsDS1244/DS1244P256k NV SRAMwith Phantom Clock
DS1244Y-70 ,256k NV SRAM with phantom clock, 70nsFEATURES PIN ASSIGNMENT (Top View) Real-time clock (RTC) keeps track ofVCC1 28A14/RSThundredths of ..
DS1244Y-70+ ,256k NV SRAM with Phantom ClockFEATURES PIN CONFIGURATIONS Real-Time Clock (RTC) Keeps Track of TOP VIEW Hundredths of Seconds, ..
DS1245 ,3.3V 1024k Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theNC 32 V1 CCabsence of external power ..
DS1245AB ,1024k Nonvolatile SRAM19-5638; Rev 11/10 DS1245Y/AB 1024k Nonvolatile SRAM www .maxim-ic.com
DS1245AB-100 ,1024K Nonvolatile SRAMDS1245Y/AB1024k Nonvolatile SRAMwww.dalsemi.com
DTA144WS , DTA/DTC SERIES
DTA144WSA , Digital transistors (built-in resistors)
DTB113EK , -500mA / -50V Digital transistors (with built-in resistors)
DTB113ES , Digital transistors (built-in resistors)
DTB113ZS , Digital transistors (built-in resistors)
DTB114GK , −500mA / −50V Digital transistors (with built-in resistors)
DS1244W-120IND-DS1244WP-120-DS1244Y-70
256k NV SRAM with phantom clock, 120ns
FEATURESReal-time clock (RTC) keeps track of
hundredths of seconds, minutes, hours, days,
date of the month, months, and years32k x 8 NV SRAM directly replaces volatile
static RAM or EEPROMEmbedded lithium energy cell maintains
calendar operation and retains RAM dataWatch function is transparent to RAMoperationMonth and year determine the number of
days in each month; valid up to 2100Full 10% operating rangeOperating temperature range: 0�C to +70�COver 10 years of data retention in the
absence of powerLithium energy source is electrically
disconnected to retain freshness until poweris applied for the first timeDIP module onlyStandard 28-pin JEDEC pinoutPowerCap® module board onlySurface mountable package for directconnection to PowerCap containing
battery and crystalReplaceable battery (PowerCap)Pin-for-pin compatible with DS1248P
and DS1251PUnderwriters Laboratory (UL) recognized
PowerCap is a registered trademark of Dallas Semiconductor.
PIN ASSIGNMENT (Top View)
Package Dimension Informationhttp:///TechSupport/DallasPackInfo.htm
DS2144
28-PDIP Module (740mil)
VCC
DQ7
DQ6
DQ5
DQ3
DQ4
DQ0
DQ1
GND
DQ2N.C.
N.C.
WEDQ7DQ6
DQ4DQ3
DQ1DQ0
VCC
RST
N.C.
DQ5
DQ2
GNDN.C.
DS1244P34-Pin PowerCap Module
(Uses DS9034PCX PowerCap)
DS1244/DS1244P256k NV SRAM
with Phantom Clock
DS1244/DS1244P
PIN DESCRIPTIONA0–A14 - Address Inputs - Chip Enable - Output Enable - Write Enable
VCC- Power-Supply Input
GND - GroundDQ0–DQ7 - Data In/Data Out
N.C. - No Connection
X1, X2- Crystal Connection
VBAT- Battery Connection
RST - Reset
TYPICAL OPERATING CIRCUIT
ORDERING INFORMATIONDS9034PCX (PowerCap) Required. (Must be ordered separately.)
DESCRIPTIONThe DS1244 256k NV SRAM with a Phantom clock is a fully static nonvolatile RAM (NV SRAM)
(organized as 32k words by 8 bits) with a built-in real-time clock. The DS1244 has a self-contained
lithium energy source and control circuitry, which constantly monitors VCC for an out-of-tolerance
condition. When such a condition occurs, the lithium energy source is automatically switched on andwrite protection is unconditionally enabled to prevent garbled data in both the memory and real-time
clock.
The phantom clock provides timekeeping information for hundredths of seconds, seconds, minutes, hours,
days, date, months, and years. The date at the end of the month is automatically adjusted for months with
fewer than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or
12-hour format with an AM/PM indicator.
PACKAGESThe DS1244 is available in two packages: 28-pin DIP and 34-pin PowerCap module. The 28-pin DIP-
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1244P after the completion of the surface mount process. Mounting the PowerCap after the surfacemount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap
DS1244/DS1244P
RAM READ MODEThe DS1244 executes a read cycle whenever WE(write enable) is inactive (high) and CE (chip enable)
is active (low). The unique address specified by the 15 address inputs (A0–A14) defines which of the
32,768 bytes of data is to be accessed. Valid data is available to the eight data-output drivers within tACC
(access time) after the last address input signal is stable, providing that CE and OE (output enable)
access times and states are also satisfied. If OE and CE access times are not satisfied, then data access
must be measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for or tOE for OE, rather than address access.
RAM WRITE MODEThe DS1244 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE
active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODEThe 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power fail point, VPF (point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point, VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF.
When VCC fall as below the VPF, access to the device is inhibited. If VPF is less than VBAT, the device
power is switched from VCC to the backup supply (VBAT ) when VCC drops below VPF. If VPF is greater
than VBAT, the device power is switched from VCC to the backup supply (VBAT ) when VCC drops below
VBAT. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal
levels.
All control, data, and address signals must be powered down when VCC is powered down.
PHANTOM CLOCK OPERATIONCommunication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.
DS1244/DS1244P
the CE and OE control of the phantom clock starts the pattern recognition sequence by moving a pointer
to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the
phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write
cycles generated to gain access to the phantom clock are also writing data to a location in the mated
RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a
phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit
comparison register. If a match is found, the pointer increments to the next location of the comparison
register and awaits the next write cycle. If a match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the
present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues fortotal of 64 write cycles as described above until all the bits in the comparison register have been
matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data transfer to or
from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either
receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other
locations outside the memory block can be interleaved with CE cycles without interrupting the pattern
recognition sequence or data transfer sequence to the phantom clock.
PHANTOM CLOCK REGISTER INFORMATIONThe phantom clock information is contained in eight registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating
the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the phantom clock register is in binary coded decimal (BCD) format. Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
DS1244/DS1244P
Figure 1. PHANTOM CLOCK REGISTER DEFINITION
Note: The pattern recognition in hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern beingaccidentally duplicated and causing inadvertent entry to the phantom clock is less than 1 in 1019. This
pattern is sent to the phantom clock LSB to MSB.
DS1244/DS1244P
Figure 2. PHANTOM CLOCK REGISTER DEFINITION
AM/PM/12/24 MODEBit 7 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour
mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour
mode, bit 5 is the second 10-hour bit (20–23 hours).
OSCILLATOR AND RESET BITSBits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the
RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET
bit is set to logic 0, a low input on the RESET pin will cause the phantom clock to abort data transfer
without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the
oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These
bits are shipped from the factory set to a logic 1.
ZERO BITSRegisters 1, 2, 3, 4, 5, and 6 contain one or more bits that always read logic 0. When writing these
DS1244/DS1244P
BATTERY LONGEVITYThe DS1244 has a lithium power source that is designed to provide energy for clock activity and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1244 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25�C with the internal clock oscillator running
in the absence of VCC power. Each DS1244 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF , the lithium energy source is enabled for battery-backup operation. Actual life expectancy of the
DS1244 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.
See “Conditions of Acceptability” at http:///TechSupport/QA/ntrl.htm.
CLOCK ACCURACY (DIP MODULE)The DS1244 is guaranteed to keep time accuracy to within �1 minute per month at +25�C. The clock is
calibrated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements
and does not require additional calibration. For this reason, methods of field clock calibration are not
available and not necessary.
CLOCK ACCURACY (POWERCAP MODULE)The DS1244P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within �1.53 minutes per month (35ppm) at +25�C.
DS1244/DS1244P
ABSOLUTE MAXIMUM RATINGS*Voltage Range on Any Pin Relative to Ground -0.3V to +6.0V
Storage Temperature Range-40ºC to +85ºC
Soldering Temperature RangeSee IPC/JEDEC J-STD-020A (DIP)(Note 13)
OPERATING RANGE*This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED DC OPERATING CONDITIONS Over the operating range
DC ELECTRICAL CHARACTERISTICS Over the operating range (5V)
DS1244/DS1244P
DC ELECTRICAL CHARACTERISTICS Over the operating range (3.3V)
CAPACITANCE (TA = +25°C)
MEMORY AC ELECTRICAL CHARACTERISTICS Over the operating range (5V)
DS1244/DS1244P
PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICSOver the operating range (5V)
POWER-DOWN/POWER-UP TIMINGOver the operating range (5V)
(TA = +25°C)
Warning: Under no circumstances are negative undershoots of any amplitude allowed when device is inbattery-backup mode.
