DS1244Y-70+ ,256k NV SRAM with Phantom ClockFEATURES PIN CONFIGURATIONS Real-Time Clock (RTC) Keeps Track of TOP VIEW Hundredths of Seconds, ..
DS1245 ,3.3V 1024k Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theNC 32 V1 CCabsence of external power ..
DS1245AB ,1024k Nonvolatile SRAM19-5638; Rev 11/10 DS1245Y/AB 1024k Nonvolatile SRAM www .maxim-ic.com
DS1245AB-100 ,1024K Nonvolatile SRAMDS1245Y/AB1024k Nonvolatile SRAMwww.dalsemi.com
DS1245AB-100+ ,1024k Nonvolatile SRAM19-5638; Rev 11/10 DS1245Y/AB 1024k Nonvolatile SRAM www .maxim-ic.com
DS1245AB-120 ,1024K Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theNC 32 V1 CCabsence of external power ..
DTA144WS , DTA/DTC SERIES
DTA144WSA , Digital transistors (built-in resistors)
DTB113EK , -500mA / -50V Digital transistors (with built-in resistors)
DTB113ES , Digital transistors (built-in resistors)
DTB113ZS , Digital transistors (built-in resistors)
DTB114GK , −500mA / −50V Digital transistors (with built-in resistors)
DS1244W-120+-DS1244W-120IND+-DS1244WP-120+-DS1244Y-70+
256k NV SRAM with Phantom Clock
FEATURES Real-Time Clock (RTC) Keeps Track of
Hundredths of Seconds, Minutes, Hours,
Days, Date of the Month, Months, and Years 32K x 8 NV SRAM Directly Replaces
Volatile Static RAM or EEPROM Embedded Lithium Energy Cell Maintains
Calendar Operation and Retains RAM Data Watch Function is Transparent to RAM
Operation Automatic Leap Year Compensation Valid
Up to 2100 Full 10% Operating Range Over 10 Years of Data Retention in the
Absence of Power Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time DIP Module Only Standard 28-Pin JEDEC Pinout PowerCap Module Board Only Surface Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal Replaceable Battery (PowerCap) Pin-for-Pin Compatible with DS1248P
and DS1251P Underwriters Laboratories (UL) Recognized
PIN CONFIGURATIONS
EDIP Module
(740 mils) VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
10
11
12
14
13
28
27
26
25
24
23
22
21
20
19
18
17
15
16
A14/RST
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
GND
DQ2 N.C.
N.C.
WE
CE DQ7
DQ6
DQ4
DQ3
DQ1
DQ0
10
11
12
14
15
16
N.C. 33 32
31
29
27
25 24
22 21
20
18
A12 A11
A9 A8
A6
A5
A2
A4
A0
VCC
28
A1
RST 2
N.C.
OE
DQ5
DQ2
GND
13
17
A14
30
26
23
19
A13
A10
A7
A3
34 N.C.
X1 GND VBAT X2
PowerCap Module
(Uses DS9034PCX+ PowerCap) TOP VIEW
DS1244P
DS1244
DS1244/DS1244P
256K NV SRAM with Phantom Clock
19-6077; Rev 11/11
DS1244/DS1244P
TYPICAL OPERATING CIRCUIT
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE VOLTAGE
(V) DS1244W-120+ 0°C to +70°C 28 EDIP (0.740a) 3.3
DS1244W-120IND+ -40°C to +85°C 28 EDIP (0.740a) 3.3
DS1244WP-120+ 0°C to +70°C 34 PowerCap* 3.3
DS1244WP-120IND+ -40°C to +85°C 34 PowerCap* 3.3
DS1244Y-70+ 0°C to +70°C 28 EDIP (0.740a) 5.0
DS1244YP-70+ 0°C to +70°C 34 PowerCap* 5.0
+Denotes a lead(Pb)-free/RoHS-compliant device.
*DS9034PCX+ or DS9034I-PCX+ (PowerCap) required. (Must be ordered separately.)
DS1244/DS1244P
PIN DESCRIPTION
PIN NAME FUNCTION EDIP PowerCap 1 A14/RST
Address Input/Active-Low Reset Input. This pin has an internal
pullup resistor connected to VCC. A14 address on the EDIP
package. 32 A14
Address Inputs 30 A12 25 A7 24 A6 23 A5 22 A4 21 A3 20 A2 19 A1
10 18 A0
21 28 A10
23 29 A11
24 27 A9
25 26 A8
26 31 A13
11 16 DQ0
Data In/Data Out
12 15 DQ1
13 14 DQ2
15 13 DQ3
16 12 DQ4
17 11 DQ5
18 10 DQ6
19 9 DQ7
20 8 CE Active-Low Chip-Enable Input
22 7 OE Active-Low Output-Enable Input
27 6 WE Active-Low Write-Enable Input 2, 3, 4, 33,
34 N.C. No Connection
28 5 VCC Power-Supply Input
14 17 GND Ground
DS1244/DS1244P
DESCRIPTION The DS1244 256K NV SRAM with a Phantom clock is a fully static nonvolatile RAM (NV SRAM)
(organized as 32K words by 8 bits) with a built-in real-time clock. The DS1244 has a self-contained
lithium energy source and control circuitry, which constantly monitors VCC for an out-of-tolerance
condition. When such a condition occurs, the lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent garbled data in both the memory and real-time
clock.
The phantom clock provides timekeeping information for hundredths of seconds, seconds, minutes, hours,
days, date, months, and years. The date at the end of the month is automatically adjusted for months with
fewer than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or
12-hour format with an AM/PM indicator.
PACKAGES The DS1244 is available in two packages: 28-pin encapsulated DIP and 34-pin PowerCap module. The
28-pin DIP-style module integrates the crystal, lithium energy source, and silicon all in one package. The
34-pin PowerCap module board is designed with contacts for connection to a separate PowerCap
(DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on
top of the DS1244P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to the high temperatures required
for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and
PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap
is DS9034PCX.
RAM READ MODE The DS1244 executes a read cycle whenever WE(write enable) is inactive (high) and CE (chip enable)
is active (low). The unique address specified by the 15 address inputs (A0–A14) defines which of the
32,768 bytes of data is to be accessed. Valid data is available to the eight data-output drivers within tACC
(access time) after the last address input signal is stable, providing that CE and OE (output enable)
access times and states are also satisfied. If OE and CE access times are not satisfied, then data access
must be measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for or tOE for OE, rather than address access.
RAM WRITE MODE The DS1244 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE
active) then WE will disable the outputs in tODW from its falling edge.
DS1244/DS1244P
DATA RETENTION MODE The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power fail point, VPF (point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point, VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF.
When VCC fall as below the VPF, access to the device is inhibited. If VPF is less than VBAT, the device
power is switched from VCC to the backup supply (VBAT ) when VCC drops below VPF. If VPF is greater
than VBAT, the device power is switched from VCC to the backup supply (VBAT ) when VCC drops below
VBAT. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal
levels.
All control, data, and address signals must be powered down when VCC is powered down.
PHANTOM CLOCK OPERATION Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of the chip enable, output enable, and write enable. Initially, a read cycle to any memory location using
the CE and OE control of the phantom clock starts the pattern recognition sequence by moving a pointer
to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the
phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write
cycles generated to gain access to the phantom clock are also writing data to a location in the mated
RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a
phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit
comparison register. If a match is found, the pointer increments to the next location of the comparison
register and awaits the next write cycle. If a match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the
present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for
a total of 64 write cycles as described above until all the bits in the comparison register have been
matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data transfer to or
from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either
receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other
locations outside the memory block can be interleaved with CE cycles without interrupting the pattern
DS1244/DS1244P
PHANTOM CLOCK REGISTER INFORMATION The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating
the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the phantom clock register is in binary coded decimal (BCD) format. Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
Figure 1. PHANTOM CLOCK REGISTER DEFINITION
NOTE: THE PATTERN RECOGNITION IN HEX IS C5, 3A, A3, 5C, C5, 3A, A3, 5C. THE ODDS OF THIS PATTERN BEING ACCIDENTALLY DUPLICATED AND CAUSING INADVERTENT ENTRY TO THE PHANTOM CLOCK IS LESS THAN 1 IN
1019. THIS PATTERN IS SENT TO THE PHANTOM CLOCK LSB TO MSB.
DS1244/DS1244P
Figure 2. PHANTOM CLOCK REGISTER DEFINITION
AM/PM/12/24 MODE Bit 7 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour
mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour
mode, bit 5 is the 20-hour bit (20–23 hours).
OSCILLATOR AND RESET BITS Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the
RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET
bit is set to logic 0, a low input on the RESET pin will cause the phantom clock to abort data transfer
without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the
oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These
bits are shipped from the factory set to a logic 1.
ZERO BITS
DS1244/DS1244P
BATTERY LONGEVITY The DS1244 has a lithium power source that is designed to provide energy for clock activity and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1244 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running
in the absence of VCC power. Each DS1244 is shipped from Maxim with its lithium energy source
disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF , the
lithium energy source is enabled for battery-backup operation. Actual life expectancy of the DS1244 will
be much longer than 10 years since no lithium battery energy is consumed when VCC is present.
See “Conditions of Acceptability” at /TechSupport/QA/ntrl.htm.
CLOCK ACCURACY (DIP MODULE) The DS1244 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The clock is
calibrated at the factory by Maxim using special calibration nonvolatile tuning elements and does not
require additional calibration. For this reason, methods of field clock calibration are not available and not
necessary.
CLOCK ACCURACY (POWERCAP MODULE) The DS1244P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35ppm) at +25°C.
DS1244/DS1244P
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground (5V product) ………………………..-0.3V to +6.0V (3.3V product) ……………………..-0.3V to +4.6V
Storage Temperature Range EDIP ………………………………………………………….……………………-40ºC to +85ºC PowerCap …………………………………………………………………………-55ºC to +125ºC
Lead Temperature (soldering, 10 seconds) ……………………………………………………… +260ºC
Note: EDIP is wave or hand-soldered only. Soldering Temperature (reflow, PowerCap) …………………………………………………… +260ºC
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect
reliability.
OPERATING RANGE
RANGE TEMP RANGE
(NONCONDENSING) VCC Commercial 0°C to +70°C 3.3V ±10% or 5V ±10%
Industrial -40°C to +85°C 3.3V ±10% or 5V ±10%
RECOMMENDED OPERATING CONDITIONS Over the operating range
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Logic 1
VCC = 5V ±10%
VIH
2.2 VCC + 0.3 11
VCC = 3.3V ±10% 2.0 VCC + 0.3
Input Logic 0
VCC = 5V ±15%
VIL
-0.3 0.8 11
VCC = 3.3V ±10% -0.3 0.6
DC ELECTRICAL CHARACTERISTICS Over the operating range (5V) 0BPARAMETER
SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current IIL -1.0 +1.0 µA 12
I/O Leakage Current ≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current at 2.4V IOH -1.0 mA
Output Current at 0.4V IOL 2.0 mA
Standby Current CE = 2.2V ICCS1 5 10 mA
Standby Current = VCC - 0.5V ICCS2 3.0 5.0 mA
Operating Current tCYC = 70ns ICC01 85 mA
Write Protection Voltage VPF 4.25 4.37 4.50 V 11
Battery Switchover Voltage VSO VBAT 7BV 11
DS1244/DS1244P
DC ELECTRICAL CHARACTERISTICS Over the operating range (3.3V) 1BPARAMETER
SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current IIL -1.0 +1.0 µA 12
I/O Leakage Current ≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current at 2.4V IOH -1.0 mA
Output Current at 0.4V IOL 2.0 mA
Standby Current CE = 2.2V ICCS1 5 7 mA
Standby Current = VCC - 0.5V ICCS2 2.0 3.0 mA
Operating Current tCYC = 70ns ICC01 50 mA
Write Protection Voltage VPF 2.80 2.86 2.97 V 11
Battery Switchover Voltage VSO VBAT or VPF 8BV 11
CAPACITANCE (TA = +25°C) 2BPARAMETER
SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance CIN 5 10 pF
Input/Output Capacitance CI/O 5 10 pF
MEMORY AC ELECTRICAL CHARACTERISTICS Over the operating range (5V)
PARAMETER SYMBOL 9BDS1244Y-70
3BUNITS 4BNOTES
10BMIN 11BMAX
Read Cycle Time tRC 70 ns
Access Time tACC 70 ns to Output Valid tOE 35 ns to Output Valid tCO 70 ns or CE to Output Active tCOE 5 ns 5
Output High-Z from Deselection tOD 25 ns 5
Output Hold from Address Change tOH 5 ns
Write Cycle Time tWC 70 ns
Write Pulse Width tWP 50 ns 3
Address Setup Time tAW 0 ns
Write Recovery Time tWR 0 ns
Output High-Z from WE tODW 25 ns 5
Output Active from WE tOEW 5 ns 5
Data Setup Time tDS 30 ns 4
Data Hold Time from WE tDH 5 ns 4
