DS1243Y-120+ ,64K NV SRAM with Phantom ClockFEATURES PIN CONFIGURATION Real-Time Clock Keeps Track of Hundredths TOP VIEW of Seconds, Secon ..
DS1243Y-150 ,64K NV SRAM with Phantom ClockDS1243Y64K NV SRAM with Phantom Clockwww.dalsemi.comPIN ASSIGNMENT
DS1244W-120+ ,256k NV SRAM with Phantom ClockFEATURES PIN CONFIGURATIONS Real-Time Clock (RTC) Keeps Track of TOP VIEW Hundredths of Seconds, ..
DS1244W-120IND ,256k NV SRAM with phantom clock, 120nsFEATURES PIN ASSIGNMENT (Top View) Real-time clock (RTC) keeps track ofVCC1 28A14/RSThundredths of ..
DS1244W-120IND+ ,256k NV SRAM with Phantom ClockFEATURES PIN CONFIGURATIONS Real-Time Clock (RTC) Keeps Track of TOP VIEW Hundredths of Seconds, ..
DS1244WP-120 ,256k NV SRAM with phantom clock, 120nsDS1244/DS1244P256k NV SRAMwith Phantom Clock
DTA144WE ,Bias Resistor TransistorDTA114EET1 SeriesPreferred DevicesBias Resistor TransistorsPNP Silicon Surface Mount Transistorswit ..
DTA144WET1 ,Bias Resistor Transistordevice and its external resistor bias network. The Bias ResistorTransistor (BRT) contains a single ..
DTA144WF , DTA/DTC SERIES
DTA144WS , DTA/DTC SERIES
DTA144WSA , Digital transistors (built-in resistors)
DTB113EK , -500mA / -50V Digital transistors (with built-in resistors)
DS1243Y-120+
64K NV SRAM with Phantom Clock
FEATURES Real-Time Clock Keeps Track of Hundredths
of Seconds, Seconds, Minutes, Hours, Days,
Date of the Month, Months, and Years 8K x 8 NV SRAM Directly Replaces
Volatile Static RAM or EEPROM Embedded Lithium Energy Cell Maintains
Calendar Operation and Retains RAM Data Watch Function is Transparent to RAM
Operation Automatic Leap Year Compensation Valid
Up to 2100 Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time Standard 28-Pin JEDEC Pinout Full ±10% Operating Range Accuracy is Better than ±1 Minute/Month at
+25°C Over 10 Years of Data Retention in the
Absence of Power Available in 120ns Access Time Underwriters Laboratories (UL) Recognized
(/qa/info/ul)
PIN CONFIGURATION
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS1243Y-120+ 0°C to +70°C 28 EDIP (0.720a)
+ Denotes a lead(Pb)-free/RoHS-compliant package.
Encapsulated Package
(720-Mil Extended) A7
A5
A3
A2
A1
A0
DQ0
DQ1
GND
DQ2
VCC
WE
N.C.
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
10
11
12
14
13
28
27
26
25
24
23
22
21
20
19
18
17
15
16 A12
A6
A4
RST
DS1243Y TOP VIEW
DS1243Y
64K NV SRAM with Phantom Clock 19-6076; Rev 11/11
DS1243Y
PIN DESCRIPTION
PIN NAME FUNCTION RST Active-Low Reset Input. This pin has an internal pullup resistor
connected to VCC. A12
Address Inputs A7 A6 A5 A4 A3 A2 A1
10 A0
23 A11
21 A10
24 A9
25 A8
11 DQ0
Data In/Data Out
12 DQ1
13 DQ2
15 DQ3
16 DQ4
17 DQ5
18 DQ6
19 DQ7
20 CE Active-Low Chip-Enable Input
22 OE Active-Low Output-Enable Input
26 N.C. No Connection
27 WE Active-Low Write-Enable Input
28 VCC Power-Supply Input
14 GND Ground
DESCRIPTION The DS1243Y 64K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 8192
words by 8 bits) with a built-in real time clock. The DS1243Y has a self-contained lithium energy source
and control circuitry, which constantly monitors VCC for an out-of-tolerance condition. When such a
condition occurs, the lithium energy source is automatically switched on and write protection is
unconditionally enabled to prevent corrupted data in both the memory and real time clock. The Phantom
Clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, day,
date, month, and year information. The date at the end of the month is automatically adjusted for months
with fewer than 31 days, including correction for leap years. The Phantom Clock operates in either
24-hour or 12-hour format with an AM/PM indicator.
DS1243Y
RAM READ MODE The DS1243Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) is active (low). The unique address specified by the 13 address inputs (A0–A12) defines which of
the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers
within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output
Enable) access times and states are also satisfied. If OE and CE access times are not satisfied, then data
access must be measured from the later occurring signal (CE or OE) and the limiting parameter is either
tCO for CE or tOE for OE rather than address access.
RAM WRITE MODE The DS1243Y is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active)
then WE will disable the outputs in t ODW from its falling edge.
DATA RETENTION MODE The DS1243Y provides full functional capability for VCC greater than VTP and write protects by 4.25V.
Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static
RAM constantly monitors VCC. Should the supply voltage decay, the RAM automatically write protects
itself. All inputs to the RAM become “don’t care” and all outputs are high impedance. As VCC falls below
approximately 3.0V, the power switching circuit connects the lithium energy source to RAM to retain
data. During power-up, when VCC rises above approximately 3.0V, the power switching circuit connects
external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume
after VCC exceeds 4.5V.
See “Conditions of Acceptability” at /TechSupport/QA/ntrl.htm
FRESHNESS SEAL Each DS1243Y is shipped from Maxim with its lithium energy source disconnected, insuring full energy
capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is enabled for
battery backup operation.
DS1243Y
PHANTOM CLOCK OPERATION Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of 64
bits which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0.
All accesses which occur prior to recognition of the 64–bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
Phantom Clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of Chip Enable (CE), Output Enable (OE), and Write Enable (WE). Initially, a read cycle to any memory
location using the CE and OE control of the Phantom Clock starts the pattern recognition sequence by
moving a pointer to the first bit of the 64–bit comparison register. Next, 64 consecutive write cycles are
executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain
access to the Phantom Clock. Therefore, any address to the memory in the socket is acceptable. However,
the write cycles generated to gain access to the Phantom Clock are also writing data to a location in the
mated RAM. The preferred way to manage this requirement is to set aside just one address location in
RAM as a Phantom Clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of
the 64–bit comparison register. If a match is found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance
and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,
the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues
for a total of 64 write cycles as described above until all the bits in the comparison register have been
matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the Phantom Clock is
enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause
the Phantom Clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without
interrupting the pattern recognition sequence or data transfer sequence to the Phantom Clock.
PHANTOM CLOCK REGISTER INFORMATION The Phantom Clock information is contained in 8 registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64–bit pattern recognition sequence has been completed. When updating
the Phantom Clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the Phantom Clock register is in binary coded decimal format (BCD). Reading and
writing the registers is always accomplished by stepping through all 8 registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
DS1243Y
PHANTOM CLOCK REGISTER DEFINITION Figure 1
NOTE: THE PATTERN RECOGNITION IN HEX IS C5, 3A, A3, 5C, C5, 3A, A3, 5C. THE ODDS OF THIS PATTERN BEING ACCIDENTALLY DUPLICATED AND CAUSING INADVERTENT ENTRY TO THE PHANTOM
CLOCK IS LESS THAN 1 IN 1019. THIS PATTERN IS SENT TO THE PHANTOM CLOCK LSB TO MSB.
DS1243Y
PHANTOM CLOCK REGISTER DEFINITION Figure 2
AM-PM/12/24 MODE Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode
is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode,
bit 5 is the 20-hour bit (20–23 hours).
OSCILLATOR AND RESET BITS Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the
RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET
bit is set to logic 0, a low input on the RESET pin will cause the Phantom Clock to abort data transfer
without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the
oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These
bits are shipped from the factory set to a logic 1, oscillator off.
ZERO BITS
DS1243Y
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-0.3V to +6.0V
Operating Temperature Range……………………………………………...0°C to +70°C (noncondensing)
Storage Temperature Range……………………………………………...-40°C to +85°C (noncondensing)
Lead Temperature (soldering, 10s)……… . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C
Note: EDIP is wave or hand-soldered only. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (TA = 0°C to +70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Power Supply Voltage VCC 4.5 5.0 5.5 V
Input Logic 1 VIH 2.2 VCC+0.3 V
Input Logic 0 VIL -0.3 +0.8 V
DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±10%, TA = 0°C to +70°C.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current IIL -1.0 +1.0 µA 12
I/O Leakage Current ≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current @ 2.4V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
Standby Current CE = 2.2 ICCS1 5.0 10 mA
Standby Current CE = VCC – 0.5V ICCS2 3.0 5.0 mA
Operating Current tCYC = 200ns ICC01 85 mA
Write Protection Voltage VTP 4.25 4.5 V
DC TEST CONDITIONS Outputs are open; all voltages are referenced to ground.
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance CIN 5 10 pF
Input/Output Capacitance CI/O 5 10 pF
