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DS1238A-10-DS1238A-5+
MicroManager
FEATURESHolds microprocessor in check during power
transientsHalts and restarts an out-of-controlmicroprocessorWarns microprocessor of an impending power
failureConverts CMOS SRAM into nonvolatile
memoryUnconditionally write protects memory when
power supply is out of toleranceDelays write protection until completion of
the current memory cycleConsumes less than 200 nA of battery currentControls external power switch for high
current applicationsDebounces pushbutton resetAccurate 10% power supply monitoringOptional 5% power supply monitoringdesignated DS1238A-5Provides orderly shutdown in microprocessor
applicationsPin-for-pin compatible with MAX691Standard 16-pin DIP or space-saving 16-pinSOICOptional industrial temperature range -40°C
to +85°C
PIN ASSIGNMENT
PIN DESCRIPTIONVBAT - +3-Volt Battery Input
VCCO - Switched SRAM Supply Output
VCC - +5-Volt Power Supply Input
GND - Ground
PF - Power-Fail
RVT - Reset Voltage ThresholdOSCIN - Oscillator In
OSCSEL- Oscillator Select
IN - Early Warning Input
NMI - Non-Maskable Interrupt - Strobe Input
CEO - Chip Enable Output
CEI - Chip Enable Input
WDS - Watchdog Status
RST - Reset Output (active low)
RST- Reset Output (active high)
DESCRIPTIONThe DS1238A MicroManager provides all the necessary functions for power supply monitoring, reset
control, and memory backup in microprocessor-based systems. A precise internal voltage reference and
comparator circuit monitor power supply status. When an out-of-tolerance condition occurs, themicroprocessor reset and power-fail outputs are forced active, and static RAM control unconditionally
16-Pin SOIC (300-mil)
See Mech. Drawings Section
VBAT
VCCO
VCC
RST
RST
WDS
GNDCEI
RVT
OSCIN
CEO
NMI
OSCSELIN
16-Pin DIP (300-mil)
See Mech. Drawings Section
VBAT
VCCO
VCC
RST
RST
WDS
GNDCEI
RVT
OSCIN
CEO
NMI
OSCSELIN
DS1238A
debounce circuit connected to the RST pin. An internal watchdog timer can also force the reset outputs to
the active state if the strobe input is not driven low prior to watchdog timeout. Oscillator control pins
OSCSEL and OSCIN provide either external or internal clock timing for both the reset pulse width and
the watchdog timeout period. The Watchdog Status and Reset Voltage Threshold are provided via WDS
and RVT, respectively. A block diagram of the DS1238A is shown in NO TAG.
PIN DESCRIPTION
POWER MONITORThe DS1238A employs a bandgap voltage reference and a precision comparator to monitor the 5-volt
supply (VCC) in microprocessor-based systems. When an out-of-tolerance condition occurs, the RVT,
RST, and RST outputs are driven to the active state. The VCC trip point (VCCTP) is set for 10% operation
so that the RVT, RST and RST outputs will become active as VCC falls below 4.5 volts (4.37 typical).
The VCCTP for the 5% operation option (DS1238A-5) is set for 4.75 volts (4.62 typical). The RST and
RST signals are excellent for microprocessor reset control, as processing is stopped at the last possible
moment of in-tolerance VCC. On power-up, RVT will become inactive as soon as VCC rises above VCCTP.
However, the RST and RST signals remain active for a minimum of 50 ms (100 ms typical) after VCCTP is
reached to allow the power supply and microprocessor to stabilize.
DS1238A
DS1238A FUNCTIONAL BLOCK DIAGRAM Figure 1
WATCHDOG TIMERThe DS1238A provides a watchdog timer function which forces the WDS, RST, and RST signals to the
active state when the strobe input (ST) is not stimulated for a predetermined time period. This time period
is described below in NO TAG. The watchdog timeout period begins as soon as RST and RST are
inactive. If a high-to-low transition occurs at the ST input prior to timeout, the watchdog timer is reset
and begins to timeout again. The ST input timing is shown in NO TAG. In order to guarantee that the
watchdog timer does not timeout, a high-to-low transition on ST must occur at or less than the minimum
DS1238A
full period as outlined in NO TAG. The WDS pin will remain low until one of three operations occurs.
The first is to strobe the ST pin with a falling edge, which will both set the WDS as well as the watchdog
timer count. The second is to leave the ST pin open, which disables the watchdog. Lastly, the WDS pin is
active low whenever VCC falls below VCCTP and activates the RVT signal. The ST input can be derived
from microprocessor address, data, or control signals, as well as microcontroller port pins. Under normal
operating conditions, these signals would routinely reset the watchdog timer prior to timeout. The
watchdog is disabled by leaving the ST input open, or as soon as VCC falls to VCCTP.
NON-MASKABLE INTERRUPTThe DS1238A generates a non-maskable interrupt (NMI) for early warning of a power failure to the
microprocessor. A precision comparator monitors the voltage level at the IN pin relative to an on-chip
reference generated by an internal band gap. The IN pin is a high-impedance input allowing for a user-defined sense point. An external resistor voltage divider network (NO TAG) is used to interface with high
voltage signals. This sense point may be derived from the regulated 5-volt supply, or from a higher DC
voltage level closer to the main system power input. Since the IN trip point VTP is 1.27 volts, the proper
values for R1 and R2 can be determined by the equation as shown in NO TAG. Proper operation of the
DS1238A requires that the voltage at the IN pin be limited to VIH. Therefore, the maximum allowablevoltage at the supply being monitored (VMAX) can also be derived as shown in NO TAG. A simple
approach to solving this equation is to select a value for R2 of high enough value to keep power
consumption low, and solve for R1. The flexibility of the IN input pin allows for detection of power loss
at the earliest point in a power supply system, maximizing the amount of time for microprocessor
shutdown between NMI and RST or RST.
When the supply being monitored decays to the voltage sense point, the DS1238A will force the NMI
output to an active state. Noise is removed from the NMI power-fail detection circuitry using built-in
time domain hysteresis. That is, the monitored supply is sampled periodically at a rate determined by an
internal ring oscillator running at approximately 30 kHz (33 μs/cycle). Three consecutive samplings of
out-of-tolerance supply (below VSENSE) must occur at the IN pin to active NMI. Therefore, the supply
must be below the voltage sense point for approximately 100 μs or the comparator will reset. In this way,power supply noise is removed from the monitoring function preventing false trips. During a power-up,
any IN pin levels below VTP detected by the comparator are disabled from reaching the NMI pin until
VCC rises to VCCTP. As a result, any potential active NMI will not be initiated until VCC reaches VCCTP.
Removal of an active low level on the NMI pin is controlled by the subsequent rise of the IN pin above
VTP. The initiation and removal of the NMI signal during power up depends on the relative voltage
relationship between VCC and the IN pin voltage. Note that a fast-slewing power supply may cause the
NMI to be virtually nonexistent on power-up. This is of no consequence, however, since an RST will be
active. The NMI voltage will follow VCC down until VCC decays to VBAT. Once VCC decays to VBAT, the
NMI pin will enter a tri-state mode.
ST INPUT TIMING Figure 2
DS1238A
OSCILLATOR CONTROLS Table 1Note that the OSCIN and OSCSEL pins are tri-stated when VCC is below VBAT.
POWER MONITOR, WATCHDOG TIMER, AND PUSHBUTTON RESET Figure 3
PUSHBUTTON RESET TIMING Figure 4
DS1238A
NON-MASKABLE INTERRUPT Figure 5VSENSE = R2
MAXVOLTAGE = 1.27
NMI FROM IN INPUT Figure 6
DS1238A
MEMORY BACKUPThe DS1238A provides all of the necessary functions required to battery back a static RAM. First, an
internal switch is provided to supply SRAM power from the primary 5-volt supply (VCC) or from an
external battery (VBAT), whichever is greater. Second, the same power-fail detection described in the
power monitor section is used to hold the chip enable output (CEO) to within 0.3 volts of VCC or to within
0.7 volts of VBAT. The output voltage diode drop from VBAT (0.7V) is necessary to prevent charging of the
battery in violation of UL standards. Write protection occurs as VCC falls below VCCTP as specified. If
CEI is low at the time power-fail detection occurs, CEO is held in its present state until CEI is returnedhigh, or the period tCE expires. This delay of write protection until the current memory cycle is completed
prevents the corruption of data. If CEO is in an inactive state at the time of VCC fail detection, CEO will
be unconditionally disabled within tCF. During nominal supply conditions CEO will follow CEI with a
maximum propagation delay of 20 ns. NO TAG shows a typical nonvolatile SRAM application.
FRESHNESS SEALIn order to conserve battery capacity during initial construction of an end system, the DS1238A provides
a freshness seal that electrically disconnects the battery. This means that upon battery attachment, the
VCCO output will remain inactive until VCC is applied. This prevents VCCO from powering other deviceswhen the battery is first attached, and VCC is not present. Once VCC is applied, the freshness seal is broken
and cannot be invoked again without subsequent removal and reattachment of the battery.
POWER SWITCHINGWhen larger operating currents are required in a battery-backed system, the internal switching devices of
the DS1238A may be too small to support the required load through VCCO with a reasonable voltage drop.For these applications, the PF output is provided to gate external power switching devices. As shown in
Figure 8, power to the load is switched from VCC to battery on power-down, and from battery to VCC on
power-up. The DS1336 is designed to use the PF output to switch between VBAT and VCC. It provides
better leakage and switchover performance than currently available discrete components. The transition
threshold for PF is set to the external battery voltage VBAT, allowing a smooth transition between sources.Any load applied to the PF pin by an external switch will be supplied by the battery. Therefore, if a
discrete switch is used, this load should be taken into consideration when sizing the battery.
NONVOLATILE SRAM Figure 7
