DS1236-10 ,MicroManager ChipFEATURES PIN ASSIGNMENT Holds microprocessor in check during powerVBAT 1 16 RSTtransients Halts a ..
DS1236-10 ,MicroManager Chipapplications.CCO CCV +5V primary power input.CCPF Power-fail indicator, active high, used for exter ..
DS1236-5 ,MicroManager ChipPIN DESCRIPTION Accurate 10% power supply monitoringV - +3-Volt Battery InputBAT Optional 5% powe ..
DS1236AS-10 ,MicroManager Chipapplications.CCO CCV +5V primary power input.CCPF Power-fail indicator, active high, used for exter ..
DS1236AS-5 ,MicroManager Chipapplications Standard 16-pin DIP or space-saving 16-pin RC - Reset ControlSOIC IN - Early Warning ..
DS1238A-10 ,MicroManagerFEATURES PIN ASSIGNMENT Holds microprocessor in check during powerVBAT 1 16 RSTtransients Halts a ..
DTA144GKA , Digital transistors (built-in resistor)
DTA144GKA , Digital transistors (built-in resistor)
DTA144GUA , Digital transistors (built-in resistor)
DTA144TE , -100mA / -50V Digital transistors (with built-in resistor)
DTA144TM , -100mA / -50V Digital transistors (with built-in resistor)
DTA144TT1 ,Bias Resistor Transistor2P POWER DISSIPATION (mW)D,DTA144TT1INFORMATION FOR USING THE SC–59 SURFACE MOUNT PACKAGEMINIMUM RE ..
DS1236-10-DS1236-5
MicroManager Chip
FEATURESHolds microprocessor in check during power
transientsHalts and restarts an out-of-controlmicroprocessorMonitors pushbutton for external overrideWarns microprocessor of an impending power
failureConverts CMOS SRAM into nonvolatilememoryUnconditionally write-protects memory when
power supply is out of toleranceConsumes less than 100 nA of battery current
at 25°CControls external power switch for high
current applicationsAccurate 10% power supply monitoringOptional 5% power supply monitoringdesignated DS1236-5Provides orderly shutdown in nonvolatile
microprocessor applicationsSupplies necessary control for low-power
“stop mode” in battery operated hand-heldapplicationsStandard 16-pin DIP or space-saving 16-pin
SOICOptional industrial temperature range -40°C
to +85°C
PIN ASSIGNMENT
PIN DESCRIPTIONVBAT - +3-Volt Battery Input
VCCO - Switched SRAM Supply Output
VCC - +5-Volt Power Supply Input
GND - Ground
PF - Power-Fail (Active High) - Power-Fail (Active Low)
WC/SC - Wake-Up Control (Sleep)
RC - Reset Control
IN - Early Warning Input
NMI - Non-Maskable Interrupt - Strobe Input
CEO - Chip Enable Output
CEI - Chip Enable Input
PBRST - Pushbutton Reset Input
RST - Reset Output (Active Low)
RST - Reset Output (Active High)
DESCRIPTIONThe DS1236 MicroManager Chip provides all the necessary functions for power supply monitoring, reset
control, and memory backup in microprocessor-based systems. A precise internal voltage reference andcomparator circuit monitor power supply status. When an out-of-tolerance condition occurs, the
microprocessor reset and power-fail outputs are forced active, and static RAM control unconditionally
DS1236
MicroManager Chip16-Pin SOIC (300-mil)
See Mech. Drawings Section
VBAT
VCCO
VCC
RST
RST
PBRST
GNDCEI
WC/SC
CEO
NMI
RCIIN
16-Pin DIP (300-mil)
See Mech. Drawings Section
VBAT
VCCO
VCC
RST
RST
PBRST
GNDCEI
WC/SC
CEO
NMIIN
DS1236
input which is debounced and activates reset outputs. An internal watchdog timer can also force the reset
outputs to the active state if the strobe input is not driven low prior to watchdog timeout. Reset control
and wake-up/sleep control inputs also provide the necessary signals for orderly shutdown and startup in
battery backup and battery operated applications. A block diagram of the DS1236 is shown in Figure 1.
PIN DESCRIPTION
PROCESSOR MODEA distinction is often made between CMOS and NMOS processor systems. In a CMOS system, power
consumption may be a concern, and nonvolatile operation is possible by battery backing both the SRAM
and the CMOS processor. All resources would be maintained in the absence of VCC. A power-down resetis not issued since the low-power mode of most CMOS processors (Stop) is terminated with a Reset. A
pulsed interrupt (NMI) is issued to allow the CMOS processor to invoke a sleep mode to save power. For
this case, a power-on reset is desirable to wake up and initialize the processor. The CMOS mode is
invoked by connecting RC to VCCO.
An NMOS processor consumes more power, and consequently may not be battery backed. In this case, itis desirable to notify the processor of a power-fail, then keep it in reset during the loss of VCC. This avoids
intermittent or aberrant operation. On power-up, the processor will continue to be reset until VCC reaches
an operational level to provide an orderly start. The NMOS mode is invoked by connecting RC to ground.
DS1236
POWER MONITORThe DS1236 employs a band gap voltage reference and a precision comparator to monitor the 5-volt
supply (VCC) in microprocessor-based systems. When an out-of-tolerance condition occurs, the RST and
RST outputs are driven to the active state. The VCC trip point (VCCTP) is set for 10% operation so that the
RST and RST outputs will become active as VCC falls below 4.5 volts (4.37 typical). The VCCTP for the
5% operation option (DS1236-5) is set for 4.75 volts (4.62 typical). The RST and RST signals are
excellent for microprocessor reset control, as processing is stopped at the last possible moment of in-
tolerance VCC. On power-up, the RST and RST signals are held active for a minimum of 25 ms (100 ms
typical) after VCCTP is reached to allow the power supply and microprocessor to stabilize. Note: The
operation described above is obtained with the reset control pin (RC) connected to GND (NMOS mode).Please review the reset control section for more information.
WATCHDOG TIMERThe DS1236 provides a watchdog timer function which forces the RST and RST signals to the active
state when the strobe input (ST) is not stimulated for a predetermined time period. This time period is 400
ms typically with a maximum time-out of 600 ms. The watchdog time-out period begins as soon as RST
and RST are inactive. If a high-to-low transition occurs at the ST input prior to time-out, the watchdog
timer is reset and begins to time out again. The ST input timing is shown in Figure 2. To guarantee the
watchdog timer does not time out, a high-to-low transition on ST must occur at or less than 100 ms
(minimum time-out) from a reset. If the watchdog timer is allowed to time out, the RST and RST outputs
are driven to the active state for 25 ms minimum. The ST input can be derived from microprocessor
address, data, and/or control signals. Under normal operating conditions, these signals would routinely
reset the watchdog timer prior to time-out. If the watchdog timer is not required, two methods have been
provided to disable it.
Permanently grounding the IN pin in the CMOS mode (RC=1) will disable the watchdog. In normal
operation with RC=1, the watchdog is disabled as soon as the IN pin is below VTP. With IN grounded, an
NMI output will occur only at power-up, or when the ST pin is strobed. As shown in the Figure 3, a
falling edge on ST will generate an NMI when IN is below VTP. This allows the processor to verify that
power is between VTP and VCCTP, as an NMI will be returned immediately after the ST strobe. The
watchdog timer is not affected by the IN pin when in NMOS mode (RC=0).
If the NMI signal is required to monitor supply voltages, the watchdog may also be disabled by leaving
the ST input open. Independent of the state of the RC pin, the watchdog is also disabled as soon as VCC
falls to VCCTP.
PUSHBUTTON RESETAn input pin is provided on the DS1236 for direct connection to a pushbutton. The pushbutton reset input
requires an active low signal. Internally, this input is pulled high by a 10k resistor whenever VCC is
greater than VBAT. The PBRST pin is also debounced and timed such that the RST and RST outputs are
driven to the active state for 25 ms minimum. This 25 ms delay begins as the pushbutton is released froma low level. A typical example of the power monitor, watchdog timer, and pushbutton reset connections
are shown in Figure 4. The PBRST input is disabled whenever the IN pin voltage level is less than VTP
and the reset control (RC) is tied high (CMOS mode). The PBRST input is also disabled whenever VCC is
below VBAT. Timing of the PBRST-generated RST is illustrated in Figure 5.
DS1236
NON-MASKABLE INTERRUPTThe DS1236 generates a non-maskable interrupt NMI for early warning of power failure to amicroprocessor. A precision comparator monitors the voltage level at the IN pin relative to a reference
generated by the internal band gap. The IN pin is a high-impedance input allowing for a user-defined
sense point. An external resistor voltage divider network (Figure 6) is used to interface with high voltage
signals. This sense point may be derived from the regulated 5-volt supply or from a higher DC voltage
level closer to the main system power input. Since the IN trip point VTP is 2.54 volts, the proper valuesfor R1 and R2 can be determined by the equation as shown in Figure 6. Proper operation of the DS1236
requires that the voltage at the IN pin be limited to VIN. Therefore, the maximum allowable voltage at the
supply being monitored (VMAX) can also be derived as shown in Figure 6. A simple approach to solving
this equation is to select a value for R2 high enough to keep power consumption low, and solve for R1.
The flexibility of the IN input pin allows for detection of power loss at the earliest point in a power
supply system, maximizing the amount of time for microprocessor shutdown between NMI and RST or
RST.
When the supply being monitored decays to the voltage sense point, the DS1236 pulses the NMI output
to the active state for a minimum of 200 μs. The NMI power-fail detection circuitry also has built-in time
domain hysteresis. That is, the monitored supply is sampled periodically at a rate determined by an
internal ring oscillator running at approximately 30 kHz (33 μs/cycle). Three consecutive samplings of
out-of-tolerance supply (below VSENSE) must occur at the IN pin to activate NMI. Therefore, the supply
must be below the voltage sense point for approximately 100 μs or the comparator will reset. In this way,power supply noise is removed from the monitoring function, preventing false trips. During a power-up,
any IN pin levels below VTP are disabled from reaching the NMI pin until VCC rises to VCCTP. As a result,
any potential NMI pulse will not be initiated until VCC reaches VCCTP.
Removal of an active low level on the NMI pin is controlled by either an internal time-out (when IN pin
is less than VTP) or by the subsequent rise of the IN pin above VTP. The initiation and removal of the NMI
signal during power-up results in an NMI pulse of from 0 μs minimum to 500 μs maximum, depending
on the relative voltage relationship between VCC and the IN pin voltage. As an example, when the IN pin
is tied to ground during power-up, the internal time-out will result in a pulse of 200 μs minimum to 500
μs maximum. In contrast, if the IN pin is tied to VCCO during power-up, NMI will not produce a pulse on
power-up. Note that a fast slewing power supply may cause the NMI to be virtually nonexistent on
power-up. This is of no consequence, however, since an RST will be active.
DS1236
DS1236 FUNCTIONAL BLOCK DIAGRAM Figure 1If the IN pin is connected to VCCO, the NMI output will pulse low as VCC decays to VCCTP in the NMOS
mode (RC=0). In the CMOS mode (RC=VCCO) the power-down of VCC out-of-tolerance at VCCTP will not
produce a pulse on the NMI pin. Given that any NMI pulse has been completed by the time VCC decays
to VCCTP, the NMI pin will remain high. The NMI voltage will follow VCC down until VCC decays to
VBAT. Once VCC decays to VBAT, the NMI pin will either remain at VOHL or enter tri-state mode as
determined by the RC pin (see “Reset Control” section).
MEMORY BACKUPThe DS1236 provides all of the necessary functions required to battery back a static RAM. First, a switch
is provided to direct SRAM power from the incoming 5-volt supply (VCC) or from an external battery
(VBAT), whichever is greater. This switched supply (VCCO) can also be used to battery back a CMOS
microprocessor. For more information about nonvolatile processor applications, review the “Reset
Control” and “Wake Control” sections. Second, the same power-fail detection described in the power
DS1236
low at the time power-fail detection occurs, CEO is held in its present state until CEI is returned high, or
the period tCE expires. This delay of write protection until the current memory cycle is completed prevents
the corruption of data. If CEO is in an inactive state at the time of VCC fail detection, CEO will be
unconditionally disabled within tCF. During nominal supply conditions CEO will follow CEI with a
maximum propagation delay of 20 ns. Figure 7 shows a typical nonvolatile SRAM application.
FRESHNESS SEALIn order to conserve battery capacity during storage and/or shipment of an end system, the DS1236
provides a freshness seal to electrically disconnect the battery. Figure 8 depicts the three pulses belowground on the IN pin required to invoke the freshness seal. The freshness seal will be disconnected and
normal operation will begin when VCC is cycled and reapplied to a level above VBAT.
To prevent negative pulses associated with noise from setting the freshness mode in system applications,
a series diode and resistor can be used to shunt noise to ground. During manufacturing, the freshness sealcan still be set by holding TP2 at -3 volts while applying the 0 to –3 volts clock to TP1.
POWER SWITCHINGWhen larger operating currents are required in a battery backed system, the 5-volt supply and battery
supply switches internal to the DS1236 may not be large enough to support the required load through
VCCO with a reasonable voltage drop. For these applications, the PF and PF outputs are provided to gateexternal power switching devices. As shown in Figure 9, power to the load is switched from VCC to
battery on power-down, and from battery to VCC on power-up. The DS1336 is designed to use the PF
output to switch between VBAT and VCC. It provides better leakage and switchover performance than
currently available discrete components. The transition threshold for PF and PF is set to the external
battery voltage VBAT, allowing a smooth transition between sources. The load applied to the PF pin from
the external switch will be supplied by the battery. Therefore, if a discrete switch is used, this load shouldbe taken into consideration when sizing the battery.
RESET CONTROLAs mentioned above, the DS1236 supports two modes of operation. The CMOS mode is used when the
system incorporates a CMOS microprocessor which is battery backed. The NMOS mode is used when a
non-battery backed processor is incorporated. The mode is selected by the RC (Reset Control) pin. The
level of this pin distinguishes timing and level control on RST, RST, and NMI outputs for volatile
processor operation versus nonvolatile battery backup or battery operated processor applications.
ST/INPUT TIMING Figure 2
DS1236
NMI/FROM ST/INPUT Figure 3
POWER MONITOR, WATCHDOG Figure 4
PUSH BUTTON RESET TIMING Figure 5
DS1236
EXAMPLE 1: 5 VOLT SUPPLY, R2 = 10k OHM, VSENSE = 4.80 VOLTS∴∴∴ 4.80 = 10kR1 = 8.9k OHM
EXAMPLE 2: 12 VOLT SUPPLY, R2 = 10k OHM, VSENSE = 9.00 VOLTS∴∴∴ 9.00 = 10kR1 = 25.4k OHM
VMAX = 2.54
NONVOLATILE SRAM Figure 7
DS1236
When the RC pin is tied to ground, the DS1236 is designed to interface with NMOS processors which do
not have the microamp currents required during a battery backed mode. Grounding the RC pin does,
however, continue to support nonvolatile backup of system SRAM memory. Nonvolatile systems
incorporating NMOS processors generally require that only the SRAM memory and/or timekeepingfunctions be battery backed. When the processor is not battery backed (RC = 0), all signals connected
from the processor to the DS1236 are disconnected from the backup battery supply, or grounded when
system VCC decays below VBAT. In the NMOS processor system, the principal emphasis is placed on
giving early warnings with NMI, then providing a continuously active RST and RST signal during
power-down while isolating the backup battery from the processor during a loss of VCC.
During power-down, NMI will pulse low for a minimum of 200 μs, and then return high. If RC is tied
low (NMOS mode), the voltage on NMI will follow VCC until VCC supply decays to VBAT, at which point
NMI will enter tri-state (see timing diagram). Also, upon VCC out-of-tolerance at VCCTP, the RST and
RST outputs are driven active and RST will follow VCC as the supply decays. On power-up, RST follows
VCC up, RST is held low, and both remain active for tRST after valid VCC. During a power-up from a VCC
voltage below VBAT, any detected IN pin levels below VTP are disabled from reaching the NMI pin until
VCC rises to VCCTP. As a result, any potential NMI pulse will not be initiated until VCC reaches VCCTP.
Removal of an active low level on the NMI pin is controlled by either an internal time-out (when the IN
pin is less than VTP), or by the subsequent rise of the IN pin above VTP. The initiation and removal of the
NMI signal results in an NMI pulse of 0 μs minimum to 500 μs maximum during power-up, depending
on the relative voltage relationship between VCC and the IN pin. As an example, when the IN pin is tied to
ground, the internal timeout will result in a pulse of 200 μs minimum to 500 μs maximum. In contrast, if
the IN pin is tied to VCCO, NMI will not produce a pulse on power-up.
Connecting the RC pin to a high (VCCO) invokes CMOS mode and provides nonvolatile support to both
the system SRAM as well as a low power CMOS processor. When using CMOS microprocessors, it ispossible to place the microprocessor into a very low-power mode termed the “stop” or “halt” mode. In
this state the CMOS processor requires only microamp currents and is fully capable of being battery
backed. This mode generally allows the CMOS microprocessor to maintain the contents of internal RAM
as well as state control of I/O ports during battery backup. The processor can subsequently be restarted by
any of several different signals. To maintain this low-power state, the DS1236 issues no NMI and/or reset
signals to the processor until it is time to bring the processor back into full operation. To support the low-
power processor battery backed mode (RC = 1), the DS1236 provides a pulsed NMI for early power
failure warning. Waiting to initiate a Stop mode until after the NMI pin has returned high will guarantee
the processor that no other active NMI or RST/RST will be issued by the DS1236 until one of twoconditions occurs: 1) Voltage on the pin rises above VTP, which activates the watchdog, or 2) VCC cycles
below then above VBAT, which also results in an active RST and RST. If VCC does not fall below VCCTP,
the processor will be restarted by the reset derived from the watchdog timer as the IN pin rises above VTP.
With the RC pin tied to VCCO, RST and RST are not forced active as VCC collapses to VCCTP. The RST is
held at a high level via the external battery as VCC falls below battery potential. This mode of operation is
intended for applications in which the processor is made nonvolatile with an external source, and allows
the processor to power down into a Stop mode as signaled from NMI at an earlier voltage level. The NMIoutput pin will pulse low for tNMI following a low voltage detect at the IN pin of VTP. Following tNMI ,
however, NMI will also be held at a high level (VBAT) by the battery as VCC decays below VBAT. On
power-up, RST and RST are held inactive until VCC reaches VBAT, then RST and RST are driven active
DS1236
additional NMI pulses. In this way, the ST pin can be used to allow the CMOS processor to determine if
the supply voltage, as monitored by the IN pin, is above or below a selected operating value. This is
illustrated in Figure 3. As discussed above, the RC pin determines the timing relationships and levels of
several signals. The following section describes the power-up and power-down timing diagrams in more
detail.
TIMING DIAGRAMSThis section provides a description of the timing diagrams shown in Figure 10, Figure 11, Figure 12, and
Figure 13. These diagrams show the relative timing and levels in both the NMOS and the CMOS mode
for power-up and down. Figure 10 illustrates the relationship for power-down in CMOS mode. As VCC
falls, the IN pin voltage drops below VTP. As a result, the processor is notified of an impending power
failure via an active NMI, which allows it to enter a sleep mode. As the power falls further, VCC crosses
VCCTP, the power monitor trip point. Since the DS1236 is in CMOS mode, no reset is generated. The RST
voltage will follow VCC down, but will fall no further than VBAT. At this time, CEO is brought high to
write protect the RAM. When the VCC reaches VBAT, a power-fail is issued via the PF and PF pins.
Figure 11 illustrates operation of the power-down sequence in NMOS mode. Once again, as power falls,
an NMI is issued. This gives the processor time to save critical data in nonvolatile SRAM. When VCC
reaches VCCTP, an active RST and RST are given. The RST voltage will follow VCC as it falls. CEO, PF,
and PF will operate in a similar manner to CMOS mode. Notice that the NMI will tri-state to prevent a
loss of battery power.
Figure 12 shows the power-up sequence for the NMOS mode. As VCC slews above VBAT, the PF and PF
pins are deactivated. An active reset occurs as well as an NMI. Although the NMI may be short due to
slew rates, reset will be maintained for the standard tRST timeout period. At a later time, if the IN pin falls
below VTP, a new NMI will occur. If the processor does not issue a ST, a watchdog reset will also occur.
The second NMI and RST are provided to illustrate these possibilities.
Figure 13 illustrates the power-up timing for CMOS mode. The principal difference is that the DS1236
issues a reset immediately in the NMOS mode. In CMOS mode, a reset is issued when IN rises above
VTP. Depending on the processor type, the NMI may terminate the Stop mode in the processor.
WAKE CONTROL/SLEEP CONTROLThe Wake/Sleep Control input (WC/SC) allows the processor to disable all comparators on the DS1236
before entering the Stop mode. This feature allows the DS1236, processor, and static RAM to maintain
nonvolatility in the lowest power mode possible. The processor may invoke the sleep mode in battery
operated applications to conserve battery capacity when an absence of activity is detected. The operationof this signal is shown in Figure 14. The DS1236 may subsequently be restarted by a high-to-low
transition on the PBRST input through human interface via a keyboard, touchpad, etc. The processor will
then be restarted as the watchdog times out and drives RST and RST active. The DS1236 can also be
started up by forcing the WC/SC pin high from an external source. Also, if the DS1236 is placed in a
sleep mode by the processor and system power is lost, the DS1236 will wake up the next time VCC rises
above VBAT. These possibilities are illustrated in Figure 15.
When the sleep mode is invoked during normal power-valid conditions, all operation on the DS1236 is
disabled, thus leaving the NMI, RST, and RST outputs disabled as well as the ST and IN inputs.
