DS1230Y-100+ ,256k Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theA14 1 28VCCabsence of external power ..
DS1230Y-120 ,256K Nonvolatile SRAMPIN DESCRIPTIONA0 - A14 - Address InputsDQ0 - DQ7 - Data In/Data OutCE - Chip EnableWE - Write Enab ..
DS1230Y-120+ ,256k Nonvolatile SRAMPIN DESCRIPTIONA0 - A14 - Address InputsDQ0 - DQ7 - Data In/Data OutCE - Chip EnableWE - Write Enab ..
DS1230Y-120IND , 256k Nonvolatile SRAM
DS1230Y-120IND+ ,256k Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theA14 1 28VCCabsence of external power ..
DS1230Y-150 ,256K Nonvolatile SRAMDS1230Y/AB256k Nonvolatile SRAMwww.dalsemi.com
DTA124ES , DTA/DTC SERIES
DTA124-ES , DTA/DTC SERIES
DTA124EUA T106 , PNP -100mA -50V Digital Transistors (Bias Resistor Built-in Transistors)
DTA124EUA T106 , PNP -100mA -50V Digital Transistors (Bias Resistor Built-in Transistors)
DTA124EUAT106 , PNP -100mA -50V Digital Transistors (Bias Resistor Built-in Transistors)
DTA124GKA , -100mA / -50V Digital transistors (with built-in resistors)
DS1230AB-100+-DS1230AB-120+-DS1230AB-120IND+-DS1230AB-150+-DS1230AB-200+-DS1230AB-70+-DS1230AB-70IND+-DS1230ABP-100-DS1230ABP-100+-DS1230ABP-70+-DS1230ABP-70IND+-DS1230Y-100+-DS1230Y-120+-DS1230Y-120IND+-DS1230Y-150+-DS1230Y-200+-DS1230Y-200IND-DS1230Y-200IND+-DS1230Y-70
256k Nonvolatile SRAM
FEATURES10 years minimum data retention in the
absence of external powerData is automatically protected during power
lossReplaces 32k x 8 volatile static RAM,
EEPROM or Flash memoryUnlimited write cyclesLow-power CMOSRead and write access times as fast as 70 nsLithium energy source is electrically
disconnected to retain freshness until power is
applied for the first timeFull �10% VCC operating range (DS1230Y)Optional �5% VCC operating range
(DS1230AB)Optional industrial temperature range of
-40�C to +85�C, designated INDJEDEC standard 28-pin DIP packagePowerCap Module (PCM) packageDirectly surface-mountable module- Replaceable snap-on PowerCap provides
lithium backup batteryStandardized pinout for all nonvolatile
SRAM productsDetachment feature on PowerCap allowseasy removal using a regular screwdriver
PIN ASSIGNMENT
PIN DESCRIPTIONA0 - A14- Address Inputs
DQ0 - DQ7 - Data In/Data Out - Chip Enable - Write Enable - Output Enable
VCC - Power (+5V)
GND - Ground
NC - No Connect
DS1230Y/AB
256k Nonvolatile SRAM28-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
A14
DQ1
DQ0
VCC
DQ7
DQ5
DQ6
A12
DQ2
GND
DQ4
DQ3NCNCNCNCVCC
WEOECEDQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0GNDNC
34-Pin POWERCAP MODULE (PCM)
(USES DS9034PC POWERCAP)
DS1230Y/AB
DESCRIPTIONThe DS1230 256k Nonvolatile SRAMs are 262,144-bit, fully static, nonvolatile SRAMs organized as
32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry
which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. DIP-package DS1230 devices can be used in place of existing 32k x 8 staticRAMs directly conforming to the popular bytewide 28-pin DIP standard. The DIP devices also match the
pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230 devices
in the Low Profile Module package are specifically designed for surface-mount applications. There is no
limit on the number of write cycles that can be executed and no additional support circuitry is required for
microprocessor interfacing.
READ MODEThe DS1230 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs(A0 - A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODEThe DS1230 devices execute a write cycle whenever the WE and CE signals are active (low) after
address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then will disable the outputs in tODW from its falling edge.
DATA RETENTION MODEThe DS1230AB provides full functional capability for VCC greater than 4.75 volts and write protects by4.5 volts. The DS1230Y provides full functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithiumenergy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1230AB and 4.5 volts for the
DS1230Y.
FRESHNESS SEALEach DS1230 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,guaranteeing full energy capacity. When VCC is first applied at a level greater than 4.25 volts, the lithium
energy source is enabled for battery back-up operation.
DS1230Y/AB
PACKAGESThe DS1230 devices are available in two packages: 28-pin DIP and 34-pin PowerCap Module (PCM).
The 28-pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a
single package with a JEDEC-standard, 600-mil DIP pinout. The 34-pin PowerCap Module integrates
SRAM memory and nonvolatile control along with contacts for connection to the lithium battery in the
DS9034PC PowerCap. The PowerCap Module package design allows a DS1230 PCM device to besurface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1230 PCM is reflow soldered, a DS9034PC PowerCap is snapped on top of the
PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper
attachment. DS1230 PowerCap Modules and DS9034PC PowerCaps are ordered separately and shipped
in separate containers. See the DS9034PC data sheet for further information.
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -0.3V to +7.0VOperating Temperature 0°C to 70°C, -40°C to +85°C for IND parts
Storage Temperature -40°C to +70°C, -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 secondsThis is a stress rating only and functional operation of the device at these or any other conditionsabove those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
DC ELECTRICAL (VCC=5V ��5% for DS1230AB)
CHARACTERISTICS (tA: See Note 10) (VCC=5V ��10% for DS1230Y)
DS1230Y/AB
CAPACITANCE (tA=25�C)
AC ELECTRICAL (VCC=5V ��5% for DS1230AB)
CHARACTERISTICS (tA: See Note 10) (VCC=5V ��10% for DS1230Y)
DS1230Y/AB
AC ELECTRICAL CHARACTERISTICS (cont'd)
DS1230Y/AB
READ CYCLESEE NOTE 1
WRITE CYCLE 1SEE NOTES 2, 3, 4, 6, 7, 8, and 12
