DS1225Y ,64K Nonvolatile SRAMPIN DESCRIPTIONA0-A12 - Address InputsDQ0-DQ7 - Data In/Data OutCE - Chip EnableWE - Write EnableOE ..
DS1225Y-150 ,64K Nonvolatile SRAMPIN DESCRIPTIONA0–A12 – Address Inputs DQ0–DQ7 – Data In/Data Out CE – Chip Enable WE – Write Enabl ..
DS1225Y-150 / ,64K Nonvolatile SRAMFEATURES PIN ASSIGNMENT• 10 years minimum data retention in the absence ofNC 1 28 VCCexternal power ..
DS1225Y-150 IND ,64K Nonvolatile SRAMPIN DESCRIPTIONA0-A12 - Address InputsDQ0-DQ7 - Data In/Data OutCE - Chip EnableWE - Write EnableOE ..
DS1225Y-150+ ,64K Nonvolatile SRAMPIN DESCRIPTIONA0-A12 - Address InputsDQ0-DQ7 - Data In/Data OutCE - Chip EnableWE - Write EnableOE ..
DS1225Y-150IND ,64K Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theVCCNC 1 28absence of external power ..
DTA123JCA ,Conductor Holdings Limited - Digital Transistor
DTA123JE ,Pre-biased TransistorsELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)ACharacteristic Symbol Min ..
DTA123JET1 ,Bias Resistor TransistorMaximum ratings applied to the device are individual stress limit values (notnormal operating condi ..
DTA123JET1G , Digital Transistors (BRT) R1 = 2.2 k, R2 = 47 k
DTA123JM , -100mA / -50V Digital transistors (with built-in resistors)
DTA123YKA , -100mA / -50V Digital transistors (with built-in resistors)
DS1225Y
64K Nonvolatile SRAM
FEATURES10 years minimum data retention in the
absence of external powerData is automatically protected during power
lossDirectly replaces 2k x 8 volatile static RAM
or EEPROMUnlimited write cyclesLow-power CMOSJEDEC standard 28-pin DIP packageRead and write access times as fast as 150 nsFull ±10% operating rangeOptional industrial temperature range of-40°C to +85°C, designated IND
PIN ASSIGNMENT24-Pin ENCAPSULATED PACKAGE
720-mil EXTENDED
PIN DESCRIPTIONA0-A12 - Address Inputs
DQ0-DQ7 - Data In/Data Out- Chip Enable- Write Enable- Output Enable
VCC - Power (+5V)
GND - Ground
DESCRIPTIONThe DS1225Y 64k Nonvolatile SRAM is a 65,536-bit, fully static, nonvolatile RAM organized as 8192words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which
constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium
energy source is automatically switched on and write protection is unconditionally enabled to prevent
data corruption. The NV SRAM can be used in place of existing 8k x 8 SRAMs directly conforming to
the popular bytewide 28-pin DIP standard. The DS1225Y also matches the pinout of the 2764 EPROM orthe 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the
number of write cycles that can be executed and no additional support circuitry is required for micro-
DS1225Y
64k Nonvolatile SRAMDQ0
DQ1
GND
DQ2
VCC
DQ7
DQ6
DQ5
DQ3
DQ4
A12
DS1225Y
READ MODEThe DS1225Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 13 address inputs(A0-A12) defines which of the 8192 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data
access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE
or tOE for OE rather than address access.
WRITE MODEThe DS1225Y executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write
cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be
kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled (CEand OEactive) then will disable the outputs in tODW from its falling edge.
DATA RETENTION MODEThe DS1225Y provides full functional capability for VCC greater than 4.5 volts and write protects at 4.25nominal. Data is maintained in the absence of VCC without any additional support circuitry. The
DS1225Y constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write
protects itself, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls
below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to
retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuitconnects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can
resume after VCC exceeds 4.5 volts.
DS1225Y
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0�C to 70�C; -40�C to +85�C for IND parts
Storage Temperature -40�C to +70�C; -40�C to +85�C for IND parts
Soldering Temperature 260�C for 10 secondsThis is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (T : See Note 10)
DC ELECTRICAL CHARACTERISTICS (TA : See Note 10; VCC = 5V ± 10%)
DS1225Y
AC ELECTRICAL CHARACTERISTICS (t A : See Note 10; VCC =5.0V ± 10%)
CAPACITANCE (T = 25�C)
DS1225Y
READ CYCLESEE NOTE 1
WRITE CYCLE 1SEE NOTE 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
DS1225Y
POWER-DOWN/POWER-UP CONDITIONSEE NOTE 11
POWER-DOWN/POWER-UP TIMING(TA = 25�C)
WARNING:Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:1. WE is high for a read cycle.
2. OE= VIH or VIL. If OE = VIH during a write cycle, the output buffers remain in a high impedance
state.
3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write
Cycle 1, the output buffers remain in a high-impedance state during this period.
