DS1225Y-150 ,64K Nonvolatile SRAMPIN DESCRIPTIONA0–A12 – Address Inputs DQ0–DQ7 – Data In/Data Out CE – Chip Enable WE – Write Enabl ..
DS1225Y-150 / ,64K Nonvolatile SRAMFEATURES PIN ASSIGNMENT• 10 years minimum data retention in the absence ofNC 1 28 VCCexternal power ..
DS1225Y-150 IND ,64K Nonvolatile SRAMPIN DESCRIPTIONA0-A12 - Address InputsDQ0-DQ7 - Data In/Data OutCE - Chip EnableWE - Write EnableOE ..
DS1225Y-150+ ,64K Nonvolatile SRAMPIN DESCRIPTIONA0-A12 - Address InputsDQ0-DQ7 - Data In/Data OutCE - Chip EnableWE - Write EnableOE ..
DS1225Y-150IND ,64K Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theVCCNC 1 28absence of external power ..
DS1225Y-150IND ,64K Nonvolatile SRAMPIN DESCRIPTIONA0-A12 - Address InputsDQ0-DQ7 - Data In/Data OutCE - Chip EnableWE - Write EnableOE ..
DTA123JE ,Pre-biased TransistorsELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)ACharacteristic Symbol Min ..
DTA123JET1 ,Bias Resistor TransistorMaximum ratings applied to the device are individual stress limit values (notnormal operating condi ..
DTA123JET1G , Digital Transistors (BRT) R1 = 2.2 k, R2 = 47 k
DTA123JM , -100mA / -50V Digital transistors (with built-in resistors)
DTA123YKA , -100mA / -50V Digital transistors (with built-in resistors)
DTA123YKA , -100mA / -50V Digital transistors (with built-in resistors)
DS1225Y-150-DS1225Y-150 /
64K Nonvolatile SRAM
DS1225Y64K Nonvolatile SRAM
DS1225Y
021998 1/8
FEATURES10 years minimum data retention in the absence of
external powerData is automatically protected during power lossDirectly replaces 8K x 8 volatile static RAM or EE-
PROMUnlimited write cyclesLow-power CMOSJEDEC standard 28–pin DIP packageRead and write access times as fast as 150 nsFull ±10% operating rangeOptional industrial temperature range of –40°C to
+85°C, designated IND
PIN ASSIGNMENTNC
A12
DQ0
DQ1
DQ2
GND
VCC
A11
A10
DQ7
DQ6
DQ5
DQ4
DQ3
28–PIN ENCAPSULATED PACKAGE
720 MIL EXTENDED
PIN DESCRIPTIONA0–A12–Address Inputs
DQ0–DQ7–Data In/Data Out –Chip Enable –Write Enable –Output Enable
VCC–Power (+5V)
GND–Ground–No Connect
DESCRIPTIONThe DS1225Y 64K Nonvolatile SRAM is a 65,536–bit,
fully static, nonvolatile RAM organized as 8192 words
by 8 bits. Each NV SRAM has a self–contained lithium
energy source and control circuitry which constantly
monitors VCC for an out–of–tolerance condition. When
such a condition occurs, the lithium energy source is
automatically switched on and write protection is uncon-
ditionally enabled to prevent data corruption. The NV
SRAM can be used in place of existing 8K x 8 SRAMs
directly conforming to the popular bytewide 28–pin DIP
standard. The DS1225Y also matches the pinout of the
2764 EPROM or the 2864 EEPROM, allowing direct
substitution while enhancing performance. There is no
limit on the number of write cycles that can be executed
and no additional support circuitry is required for micro-
processor interfacing.
DS1225Y
021998 2/8
READ MODEThe DS1225Y executes a read cycle whenever WE
(Write Enable) is inactive (high) and CE (Chip Enable)
and OE (Output Enable) are active (low). The unique
address specified by the 13 address inputs (A0–A12) de-
fines which of the 8192 bytes of data is to be accessed.
Valid data will be available to the eight data output driv-
ers within tACC (Access Time) after the last address in-
put signal is stable, providing that CE and OE access
times are also satisfied. If CE and OE access times are
not satisfied, then data access must be measured from
the later occurring signal and the limiting parameter is
either tCO for CE or tOE for OE rather than address ac-
cess.
WRITE MODEThe DS1225Y executes a write cycle whenever the WE
and CE signals are active (low) after address inputs are
stable. The latter occurring falling edge of CE or WE will
determine the start of the write cycle. The write cycle is
terminated by the earlier rising edge of CE or WE. All
address inputs must be kept valid throughout the write
cycle. WE must return to the high state for a minimum
recovery time (tWR) before another cycle can be initi-
ated. The OE control signal should be kept inactive
(high) during write cycles to avoid bus contention. How-
ever, if the output drivers are enabled (CE and OE ac-
tive) then WE will disable the outputs in tODW from its
falling edge.
DATA RETENTION MODEThe DS1225Y provides full functional capability for VCC
greater than 4.5 volts and write protects at 4.25 nominal.
Data is maintained in the absence of VCC without any
additional support circuitry. The DS1225Y constantly
monitors VCC. Should the supply voltage decay, the NV
SRAM automatically write protects itself, all inputs be-
come “don’t care,” and all outputs become high imped-
ance. As VCC falls below approximately 3.0 volts, a
power switching circuit connects the lithium energy
source to RAM to retain data. During power–up, when
VCC rises above approximately 3.0 volts, the power
switching circuit connects external VCC to RAM and dis-
connects the lithium energy source. Normal RAM oper-
ation can resume after VCC exceeds 4.5 volts.
DS1225Y
021998 3/8
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground–0.3V to +7.0V
Operating Temperature0°C to 70°C; –40°C to +85°C for IND parts
Storage Temperature–40°C to +70°C; –40°C to +85°C for IND parts
Soldering Temperature260°C for 10 secondsThis is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(tA: See Note 10)
DC ELECTRICAL CHARACTERISTICS (tA: See Note 10; VCC = 5V ± 10%)
DS1225Y
021998 4/8
AC ELECTRICAL CHARACTERISTICS(tA: See Note 10; VCC=5.0V ±10%)
CAPACITANCE(tA = 25°C)
DS1225Y
021998 5/8
ADDRESSES
DOUT
READ CYCLESEE NOTE 1
ADDRESSES
DOUT
DIN
VIH
VIL
VIL
WRITE CYCLE 1SEE NOTE 2, 3, 4, 6, 7, 8 AND 12
ADDRESSES
WRITE CYCLE 2DOUT
DIN
tWC
tWR2
VIL
VIH
VIL
SEE NOTE 2, 3, 4, 6, 7, 8 AND 13
DS1225Y
021998 6/8
POWER–DOWN/POWER–UP CONDITION3.2V
VCC
tDR
LEAKAGE CURRENT
IL SUPPLIED FROM
LITHIUM CELL
VTP
SEE NOTE 11
POWER–DOWN/POWER–UP TIMING(tA = 25°C)
WARNING:Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:WE is high for a read cycle.OE = VIH or VIL. If OE = VIH during a write cycle, the output buffers remain in a high impedance state.tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the
earlier of CE or WE going high.tDS is measured from the earlier of CE or WE going high.These parameters are sampled with a 5 pF load and are not 100% tested.If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output
buffers remain in a high impedance state during this period.If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
in a high impedance state during this period.
