DS1225AD-85 ,64K Nonvolatile SRAMDS1225AB/AD64k Nonvolatile SRAM
DS1225AD-85 ,64K Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in the1 28 VCCNCabsence of external powerA ..
DS1225AD-85+ ,64k Nonvolatile SRAMDS1225AB/AD64k Nonvolatile SRAM
DS1225Y ,64K Nonvolatile SRAMPIN DESCRIPTIONA0-A12 - Address InputsDQ0-DQ7 - Data In/Data OutCE - Chip EnableWE - Write EnableOE ..
DS1225Y-150 ,64K Nonvolatile SRAMPIN DESCRIPTIONA0–A12 – Address Inputs DQ0–DQ7 – Data In/Data Out CE – Chip Enable WE – Write Enabl ..
DS1225Y-150 / ,64K Nonvolatile SRAMFEATURES PIN ASSIGNMENT• 10 years minimum data retention in the absence ofNC 1 28 VCCexternal power ..
DTA123JCA ,Conductor Holdings Limited - Digital Transistor
DTA123JE ,Pre-biased TransistorsELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)ACharacteristic Symbol Min ..
DTA123JET1 ,Bias Resistor TransistorMaximum ratings applied to the device are individual stress limit values (notnormal operating condi ..
DTA123JET1G , Digital Transistors (BRT) R1 = 2.2 k, R2 = 47 k
DTA123JM , -100mA / -50V Digital transistors (with built-in resistors)
DTA123YKA , -100mA / -50V Digital transistors (with built-in resistors)
DS1225AB/85-DS1225AB-150+-DS1225AB-150IND+-DS1225AB-170+-DS1225AB-200-DS1225AB-200 IND-DS1225AB-200+-DS1225AB-200IND+-DS1225AB-70+-DS1225AB-70IND+-DS1225AB-85-DS1225AB-85+-DS1225AD-150+-DS1225AD-150IND+-DS1225AD-170-DS1225AD-200-DS1225AD-200+-DS1225AD-200IND+-DS1225AD
64k Nonvolatile SRAM
FEATURES10 years minimum data retention in theabsence of external powerData is automatically protected during power
lossDirectly replaces 8k x 8 volatile static RAM
or EEPROMUnlimited write cyclesLow-power CMOSJEDEC standard 28-pin DIP packageRead and write access times as fast as 70 nsLithium energy source is electricallydisconnected to retain freshness until power
is applied for the first timeFull ±10% VCC operating range (DS1225AD)Optional ±5% VCC operating range
(DS1225AB)Optional industrial temperature range of
-40°C to +85°C, designated IND
PIN ASSIGNMENT28-Pin ENCAPSULATED PACKAGE
720-mil EXTENDED
PIN DESCRIPTIONA0-A12 - Address Inputs
DQ0-DQ7 - Data In/Data Out- Chip Enable- Write Enable- Output Enable
VCC - Power (+5V)
GND - GroundNC - No Connect
DESCRIPTIONThe DS1225AB and DS1225AD are 65,536-bit, fully static, nonvolatile SRAMs organized as 8192 words
by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which
constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithiumenergy source is automatically switched on and write protection is unconditionally enabled to prevent
data corruption. The NV SRAMs can be used in place of existing 8k x 8 SRAMs directly conforming to
the popular bytewide 28-pin DIP standard. The devices also match the pinout of the 2764 EPROM and
the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the
number of write cycles that can be executed and no additional support circuitry is required formicroprocessor interfacing.
DS1225AB/AD
64k Nonvolatile SRAMDQ0
DQ1
GND
DQ2
VCC
DQ7
DQ6
DQ5
DQ3
DQ4
A12
DS1225AB/AD
READ MODEThe DS1225AB and DS1225AD execute a read cycle whenever WE(Write Enable) is inactive (high) and(Chip Enable) and OE(Output Enable) are active (low). The unique address specified by the 13address inputs (A0 -A12) defines which of the 8192 bytes of data is to be accessed. Valid data will be
available to the eight data output drivers within tACC (Access Time) after the last address input signal is
stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not
satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is
either tCO for CE or tOE for OE rather than address access.
WRITE MODEThe DS1225AB and DS1225AD execute a write cycle whenever the WE and CE signals are active
(low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the
start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address
inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum
recovery time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive
(high) during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODEThe DS1225AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1225AD provides full-functional capability for VCC greater than 4.5 volts and writeprotects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As VCC falls below approximately 3.0 volts, the power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1225AB and 4.5 volts for the
DS1225AD.
FRESHNESS SEALEach DS1225 is shipped from Dallas Semiconductor with the lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level of greater than VTP , the lithium
energy source is enabled for battery backup operation.
DS1225AB/AD
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature 0°C to 70°C; -40°C to +85°C for IND parts
Storage Temperature -40°C to +70°C; -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 secondsThis is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (T: See Note 10)
(TA: See Note 10)
(VCC =5V ± 5% for DS1225AB)
DC ELECTRICAL CHARACTERISTICS (VCC =5V ± 10% for DS1225AD)
CAPACITANCE (TA =25°C)
DS1225AB/AD
(TA: See Note 10)
(VCC =5V ± 5% for DS1225AB)
AC ELECTRICAL CHARACTERISTICS (VCC =5V ± 10% for DS1225AD)
DS1225AB/AD
AC ELECTRICAL CHARACTERISTICS (cont’d)
DS1225AB/AD
READ CYCLESEE NOTE 1
WRITE CYCLE 1SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
