DS1222 ,BankSwitch ChipPIN DESCRIPTIONA -A - Address InputsW ZCEI - Chip Enable InputCEO - Chip Enable OutputNC - No Conne ..
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DS1222
BankSwitch Chip
FEATURESProvides bank switching for 16 banks of
memoryBank switching is software-controlled by apattern recognition sequence on four address
inputsAutomatically sets all 16 banks off on
power-upBank switching logic allows only one bank onat a timeCustom recognition patterns are available to
prevent unauthorized accessFull ±10% operating rangeLow-power CMOS circuitryCan be used to expand the address range ofmicroprocessors and decodersOptional 16-pin SOIC surface mount package
PIN ASSIGNMENT
PIN DESCRIPTIONAW-AZ - Address Inputs
CEI- Chip Enable Input
CEO- Chip Enable Output
NC - No Connection
BS1,BS2, - Bank Select OutputsBS3,BS4 - Bank Select OutputsPF- Power Fail Input
VCC - +5 Volts
GND - Ground
DESCRIPTIONThe DS1222 BankSwitch Chip is a CMOS circuit designed to select one of 16 memory banks under
software control. Memory bank switching allows for an increase in memory capacity without additional
address lines. Continuous blocks of memory are enabled by selecting proper memory bank through a
pattern recognition sequence on four address inputs. Custom patterns from Dallas Semiconductor can
provide security through uniqueness and prevent unauthorized access. By combining the DS1222 with
DS1222
BankSwitch ChipDS1222 14-Pin DIPSee Mech. Drawings
Section
CEI
GND
PFI
VCC
CEO
BS1
BS2
BS3
BS4
CEI
PFI
GND
DS1222S 16-Pin SOICSee Mech. Drawings
Section
DS1222
OPERATION - BANK SWITCHINGInitially, on power-up all four bank select outputs are low and the chip enable output (CEO) is held high.
(Note: the power fail input [IFP] must be low prior to power-up to assure proper initialization.) Bank
switching is achieved by matching a predefined pattern stored within the DS1222 with a 16-bit sequence
received on four address inputs. Prior to entering the 16-bit pattern, which sets the bank switch, a read
cycle of 1111 on address inputs AW through AZ should be executed to guarantee that pattern entry starts
with bit 0. Each set of address inputs is clocked into the DS1222 when CEI is driven low. All 16 inputsmust be consecutive read cycles. The first eleven cycles must match the exact bit pattern as shown in
Table 1. The last five cycles must match the exact bit pattern as shown for addresses AX, AY, and AZ.
However, address line AW defines the bank number to be enabled as per Table 2.
Switching to a selected bank of memory occurs on the rising edge of CEI when the last set of bits is input
and a match has been established. After bank selection CEO always follows CEI with a maximum
propagation delay of 15 ns. The bank selected is determined by the levels set on Bank Select 1 throughBank Select 4 as per Table 2. These levels are held constant for all memory cycles until a new memory
bank is selected.
ADDRESS BIT SEQUENCE Table 1
X See Table 2BANK SELECT CONTROL Table 212131415BS1BS2BS3XXXXLowLowLow
DS1222
ABSOLUTE MAXIMUM RATINGS*Voltage on any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature -55°C to +125°CThis is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(0°C to 70°C)
DC ELECTRICAL CHARACTERISTICS(0°C to 70°C; VCC = 5V ±10%)
CAPACITANCE(TA = 25°C)
AC ELECTRICAL CHARACTERISTICS(0°C to 70°C; VCC = 5V ±10%)
NOTES:1. All voltages are referenced to ground.2. Measured with a load as shown in Figure 1.
DS1222
OUTPUT LOAD Figure 1
TIMING DIAGRAM-ACCESS TO BANK SWITCH
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