DS1215-DS1215. Fast Delivery |IC PHOENIX CO.,LIMITED

DS1215 ,Phantom time chipblock diagram of Figure 1 illustrates the main ele-nected memory.ments of the Time Chip. Communica ..
DS1215. ,Phantom time chipPIN DESCRIPTION(IND)X1, X2 – 32.768 KHz Crystal ConnectionsWE – Write EnableDESCRIPTIONBAT1 – Batte ..
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DS1215-DS1215.
Phantom time chip
Copyright 1997 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer toDallas Semiconductor data books.
DS1215
Phantom Time Chip
DS1215
032697 1/15
FEATURESKeeps track of hundredths of seconds, seconds, min-
utes, hours, days, date of the month, months, and
yearsAdjusts for months with fewer than 31 daysLeap year automatically corrected up to 2100No address space requiredProvides nonvolatile controller functions for battery
backup of RAMSupports redundant batteries for high–reliability
applicationsUses a 32.768 KHz watch crystalFull ±10% operating rangeOperating temperature range 0°C to 70°CSpace-saving, 16–pin DIP package and SOICOptional industrial temperature range –40°C to +85°C
(IND)
DESCRIPTION
The DS1215 Phantom Time Chip is a combination of a
CMOS timekeeper and a nonvolatile memory controller.
In the absence of power, an external battery maintains
the timekeeping operation and provides power for a
CMOS static RAM. The watch keeps track of hun-
dredths of seconds, seconds, minutes, hours, day, date,
month, and year information. The last day of the month
is automatically adjusted for months with less than 31
days, including correction for leap year every four years.
The watch operates in one of two formats: a 12–hour
mode with an AM/PM indicator or a 24–hour mode. The
nonvolatile controller supplies all the necessary support
circuitry to convert a CMOS RAM to a nonvolatile
memory. The DS1215 can be interfaced with either
RAM or ROM without leaving gaps in memory.
PIN ASSIGNMENT
BAT1
GND
GND
VCCI
VCCO
BAT2
RST
CEI
CEO
ROM/RAM
16–PIN DIP (300 MIL)
BAT1
GND
GND
VCCI
VCCO
BAT2
RST
CEI
CEO
ROM/RAM
16–PIN SOIC (300 MIL)
PIN DESCRIPTION
X1, X2–32.768 KHz Crystal Connections–Write Enable
BAT1–Battery 1 Input
GND–Ground–Data In–Data Out
ROM/RAM–ROM/RAM Select
CEO–Chip Enable Out
CEI–Chip Enable Input–Output Enable
RST–Reset
BAT2–Battery 2 Input
VCCO–Switched Supply Output
VCCI–+5 VDC Input
NOTE: Both pins 5 and 8 must be grounded.
ORDERING INFORMATION
DS121516–pin DIP
DS1215S16–pin SOIC
DS1215N16–pin DIP (IND)
DS1215SN16–pin SOIC (IND)
DS1215
032697 2/15
OPERATION
The block diagram of Figure 1 illustrates the main ele-
ments of the Time Chip. Communication with the Time
Chip is established by pattern recognition of a serial bit
stream of 64 bits which must be matched by executing
64 consecutive write cycles containing the proper data
on data in (D). All accesses which occur prior to recog-
nition of the 64-bit pattern are directed to memory via the
chip enable output pin (CEO).
After recognition is established, the next 64 read or write
cycles either extract or update data in the Time Chip and
CEO remains high during this time, disabling the con-
nected memory.
Data transfer to and from the timekeeping function is ac-
complished with a serial bit stream under control of chip
enable input (CEI), output enable (OE), and write en-
able (WE). Initially, a read cycle using the CEI and OE
control of the Time Chip starts the pattern recognition
sequence by moving a pointer to the first bit of the 64 bit
comparison register. Next, 64 consecutive write cycles
are executed using the CEI and WE control of the Time
Chip. These 64 write cycles are used only to gain ac-
cess to the Time Chip.
TIMING BLOCK DIAGRAM Figure 1VCCI
CEO
ROM/RAM
BAT1BAT2
32.768 kHz
CEI
RST
DS1215
032697 3/15
When the first write cycle is executed, it is compared to
bit 1 of the 64–bit comparison register. If a match is
found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a
match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle oc-
curs at any time during pattern recognition, the present
sequence is aborted and the comparison register point-
er is reset. Pattern recognition continues for a total of 64
write cycles as described above until all the bits in the
comparison register have been matched. (This bit pat-
tern is shown in Figure 2.) With a correct match for 64
bits, the Time Chip is enabled and data transfer to or
from the timekeeping registers may proceed. The next
64 cycles will cause the Time Chip to either receive data
on D, or transmit data on Q, depending on the level of
OE pin or the WE pin. Cycles to other locations outside
the memory block can be interleaved with CEI cycles
without interrupting the pattern recognition sequence or
data transfer sequence to the Time Chip.
A 32,768 Hz quartz crystal can be directly connected to
the DS1215 via pins 1 and 2 (X1, X2). The crystal se-
lected for use should have a specified load capacitance
(CL) of 6 pF. For more information on crystal selection
and crystal layout considerations, please consult
Application Note 58, “Crystal Considerations with Dal-
las Real Time Clocks”.
TIME CHIP COMPARISON REGISTER DEFINITION Figure 2543210
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
HEX
VALUE
NOTE:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated
and causing inadvertent entry to the Time Chip are less than 1 in 1019.
DS1215
032697 4/15
NONVOLATILE CONTROLLER OPERATION
The operation of the nonvolatile controller circuits within
the Time Chip is determined by the level of the
ROM/RAM select pin. When ROM/RAM is connected to
ground, the controller is set in the RAM mode and per-
forms the circuit functions required to make static
CMOS RAM and the timekeeping function nonvolatile.
A switch is provided to direct power from the battery in-
puts or VCCI to VCCO with a maximum voltage drop of
0.3 volts. The VCCO output pin is used to supply uninter-
rupted power to CMOS SRAM. The DS1215 also per-
forms redundant battery control for high reliability. On
power–fail, the battery with the highest voltage is auto-
matically switched to VCCO. If only one battery is used in
the system, the unused battery input should be con-
nected to ground.
The DS1215 safeguards the Time Chip and RAM data
by power–fail detection and write protection. Power–fail
detection occurs when VCCI falls below VTP, which is
equal to 1.26 x VBAT. The DS1215 constantly monitors
the VCCI supply pin. When VCCI is less than VTP, a com-
parator outputs a power–fail signal to the control logic.
The power–fail signal forces the chip enable output
(CEO) to VCCI or VBAT–0.2 volts for external RAM write
protection. During nominal supply conditions, CEO will
track CEI with a maximum propagation delay of 20 ns.
Internally, the DS1215 aborts any data transfer in prog-
ress without changing any of the Time Chip registers
and prevents future access until VCCI exceeds VTP. A
typical RAM/Time Chip interface is illustrated in
Figure 3.
When the ROM/RAM pin is connected to VCCO, the con-
troller is set in the ROM mode. Since ROM is a read–
only device that retains data in the absence of power,
battery backup and write protection is not required. As a
result, the chip enable logic will force CEO low when
power fails. However, the Time Chip does retain the
same internal nonvolatility and write protection as de-
scribed in the RAM mode. In addition, the chip enable
output is set at a low level on power–fail as VCCI falls be-
low the level of VBAT. A typical ROM/Time Chip interface
is illustrated in Figure 4.
TIME CHIP REGISTER INFORMATION
Time Chip information is contained in 8 registers of
8 bits, each of which is sequentially accessed one bit at
a time after the 64–bit pattern recognition sequence has
been completed. When updating the Time Chip regis-
ters, each must be handled in groups of 8 bits. Writing
and reading individual bits within a register could pro-
duce erroneous results. These read/write registers are
defined in Figure 5.
Data contained in the Time Chip registers is in binary
coded decimal format (BCD). Reading and writing the
registers is always accomplished by stepping though all
8 registers, starting with bit 0 of register 0 and ending
with bit 7 of register 7.
AM–PM/12/24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10–hour bit (20 –23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the
reset and oscillator functions. Bit 4 controls the reset pin
(Pin 13). When the reset bit is set to logic 1, the reset in-
put pin is ignored. When the reset bit is set to logic 0, a
low input on the reset pin will cause the Time Chip to
abort data transfer without changing data in the time-
keeping registers. Reset operates independently of all
other inputs. Bit 5 controls the oscillator. When set to
logic 0, the oscillator turns on and the watch becomes
operational.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that
will always read logic 0. When writing these locations,
either a logic 1 or 0 is acceptable.
DS1215
032697 5/15
RAM/TIME CHIP INTERFACE Figure 3
CMOS STATIC RAM
DS1215
BAT1BAT2
32.768 KHz
A0 – AN
D0 – D7
RST
OR TIE TO GND FOR
ONE–BATTERY
OPERATION
ROM/TIME CHIP INTERFACE Figure 4
ROM
DS1215
BAT1BAT212
32.768 KHz
+5 VDC
A0 – AN
D0 – D7
RST
OR TIE TO GND FOR
ONE–BATTERY
OPERATION
DS1215
032697 6/15
TIME CHIP REGISTER DEFINITION Figure 5
RANGE
(BCD)
REGISTER
00–23
DS1215
032697 7/15
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground–0.3V to +7.0V
Operating Temperature0°C to 70°C
Storage Temperature–55°C to +125°C
Soldering Temperature260°C for 10 secondsThis is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 4.5 to 5.5V)
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC < 4.5V)
DS1215
032697 8/15
AC ELECTRICAL CHARACTERISTICS ROM/RAM = GND (0°C to 70°C; VCC = 4.5 to 5.5V)
AC ELECTRICAL CHARACTERISTICS ROM/RAM = GND (0°C to 70°C; VCC > 4.5V)
CAPACITANCE (tA = 25°C)

Partno	Mfg	Dc	Qty	Available	Descript
DS1215	DALLAS	N/a	1039	avai	Phantom time chip
DS1215. \|DS1215	DAL	N/a	25	avai	Phantom time chip