DS1210+ ,Nonvolatile Controller ChipFEATURES PIN ASSIGNMENT Converts CMOS RAMs into NonvolatileVCCO 1 8VCCIMemories Unconditionally W ..
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DS1210N ,Nonvolatile Controller ChipDS1210Nonvolatile Controller Chip
DS1210S ,Nonvolatile Controller Chipapplications, data integrity is paramount. In these
DS1210S ,Nonvolatile Controller Chipapplications it is often desirable touse two batteries to ensure reliability. The DS1210 controller ..
DS1210S ,Nonvolatile Controller ChipPIN DESCRIPTIONV - RAM SupplyCCOV - + Battery 1BAT1TOL - Power Supply ToleranceGND - GroundCE - Chi ..
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DS1210+-DS1210N-DS1210S-DS1210S+-DS1210S+TRL
Nonvolatile Controller Chip
FEATURESConverts CMOS RAMs into Nonvolatile
MemoriesUnconditionally Write Protects when VCC is
Out-of-ToleranceAutomatically Switches to Battery when
Power-Fail OccursSpace-Saving 8-Pin DIPConsumes <100nA of Battery CurrentTests Battery Condition on Power upProvides for Redundant BatteriesOptional 5% or 10% Power-Fail DetectionLow Forward Voltage Drop on the VCCSwitchOptional 16-Pin SOIC Surface Mount
PackageOptional Industrial (N) Temperature Range of
-40°C to +85°C
PIN ASSIGNMENT
PIN DESCRIPTIONVCCO- RAM Supply
VBAT1- + Battery 1
TOL- Power Supply Tolerance
GND- Ground- Chip Enable Input
CEO- Chip Enable Output
VBAT2- + Battery 2
VCCI- + Supply- No Connect
DESCRIPTIONThe DS1210 Nonvolatile Controller Chip is a CMOS circuit which solves the application problem ofconverting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-of-tolerance
condition. When such a condition is detected, chip enable is inhibited to accomplish write protection and
the battery is switched on to supply the RAM with uninterrupted power. Special circuitry uses a low-
leakage CMOS process which affords precise voltage detection at extremely low battery consumption.
The 8-pin DIP package keeps PC board real estate requirements to a minimum. By combining theDS1210 Nonvolatile Controller Chip with a CMOS memory and batteries, nonvolatile RAM operation
can be achieved.
DS1210
Nonvolatile Controller ChipVCCO
VBAT1
TOL
GND
VCCI
VBAT2
CEO
DS1210 8-pin DIP (300-mil)
VCCO
VBAT1
TOL
GND
VCCI
VBAT2
CEO
DS1210S 16-pin SOIC (300-mil)
See Mech. Drawings Section
DS1210
OPERATIONThe DS1210 nonvolatile controller performs five circuit functions required to battery back up a RAM.
First, a switch is provided to direct power from the battery or the incoming supply (VCCI) depending on
which is greater. This switch has a voltage drop of less than 0.3V. The second function which the
nonvolatile controller provides is power-fail detection. The DS1210 constantly monitors the incoming
supply. When the supply goes out of tolerance a precision comparator detects power-fail and inhibits chip
enable (CEO). The third function of write protection is accomplished by holding the CEO output signal to
within 0.2 volts of the VCCI or battery supply. If CE input is low at the time power-fail detection occurs,
the CEO output is kept in its present state until CE is returned high. The delay of write protection untilthe current memory cycle is completed prevents the corruption of data. Power-fail detection occurs in the
range of 4.75 volts to 4.5 volts with the tolerance Pin 3 grounded. If Pin 3 in connected to VCCO, then
power-fail detection occurs in the range of 4.5 volts to 4.25 volts. During nominal supply conditions
CEO will follow CE with a maximum propagation delay of 20ns. The fourth function the DS1210
performs is a battery status warning so that potential data loss is avoided. Each time that the circuit is
powered up the battery voltage is checked with a precision comparator. If the battery voltage is less than2.0 volts, the second memory cycle is inhibited. Battery status can, therefore, be determined by
performing a read cycle after power-up to any location in memory, verifying that memory location
content. A subsequent write cycle can then be executed to the same memory location altering the data. If
the next read cycle fails to verify the written data, then the batteries are less than 2.0V and data is in
danger of being corrupted. The fifth function of the nonvolatile controller provides for batteryredundancy. In many applications, data integrity is paramount. In these applications it is often desirable to
use two batteries to ensure reliability. The DS1210 controller provides an internal isolation switch which
allows the connection of two batteries. During battery backup operation the battery with the highest
voltage is selected for use. If one battery should fail, the other will take over the load. The switch to a
redundant battery is transparent to circuit operation and to the user. A battery status warning will occurwhen the battery in use falls below 2.0 volts. A grounded VBAT2 pin will not activate a battery-fail
warning. In applications where battery redundancy is not required, a single battery should be connected to
the BAT1 pin. The BAT2 battery pin must be grounded. The nonvolatile controller contains circuitry to
turn off the battery backup. This is to maintain the battery(s) at its highest capacity until the equipment is
powered up and valid data is written to the SRAM. While in the freshness seal mode the CEO and VCCO
will be forced to VOL. When the batteries are first attached to one or both of the VBAT pins, VCCO will notprovide battery back-up until VCCI exceeds VCCTP, as set by the TOL pin, and then falls below VBAT.
Figure 1 shows a typical application incorporating the DS1210 in a microprocessor-based system. Section
A shows the connections necessary to write protect the RAM when VCC is less than 4.75 volts and to back
up the supply with batteries. Section B shows the use of the DS1210 to halt the processor when VCC isless than 4.75 volts and to delay its restart on power-up to prevent spurious writes.
DS1210
SECTION A - BATTERY BACKUP Figure 1
BATTERY BACKUP CURRENT DRAIN EXAMPLECONSUMPTIONDS1210 IBAT100 nA
RAM ICC0210 �A
Total Drain10.1 �A
SECTION B - PROCESSOR RESET
DS1210
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground-0.3V to +7.0V
Operating Temperature0�C to +70�C, -40�C to +85�C for N parts
Storage Temperature-55�C to +125�C
Soldering TemperatureSee IPC/JEDEC J-STD-020AThis is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(See Note 9)
DC ELECTRICAL CHARACTERISTICS(See Note 9; VCCI = 4.75 to 5.5V PIN 3 = GND)
(VCCI = 4.5 to 5.5V, PIN 3 = VCCO)
(See Note 9; VCCI = < VBAT)
DS1210
CAPACITANCE(TA = 25°C)
AC ELECTRICAL CHARACTERISTICS(See Note 9; VCCI = 4.75V to 5.5V, PIN 3 = GND)
(VCCI = 4.75V to 5.5V, PIN 3 = GND)
(See Note 9; VCCI = 4.75V, PIN 3 = GND; VCCI < 4.5, PIN 3 = VCCO)
NOTES:1. All voltages are referenced to ground.
2. Only one battery input is required. Unused battery inputs must be grounded.
3. Measured with VCCO and CEO open.
4. ICC01 is the maximum average load which the DS1210 can supply to the memories.
5. Measured with a load as shown in Figure 2.
6. ICC02 is the maximum average load current which the DS1210 can supply to the memories in the
battery backup mode.
7. tCE max. must be met to ensure data integrity on power loss.
8. CEO can only sustain leakage current in the battery backup mode.
9. All AC and DC electrical characteristics are valid for the full temperature range. For commercial
products, this range is 0 to +70�C. For industrial products (N), this range is -40�C to +85�C.
10. DS1210 is recognized by Underwriters Laboratory (U.L.®) under file E99151.
DS1210
TIMING DIAGRAM: POWER-UP
TIMING DIAGRAM: POWER-DOWN
OUTPUT LOAD Figure 2
