DS1202N ,Serial timekeeping chipPIN DESCRIPTIONDS1202N 8–pin DIP (IND)NC – No ConnectionDS1202SN 16–pin SOIC (IND)X1, X2 – 32.768 K ..
DS1202S ,Serial timekeeping chipPIN DESCRIPTIONDS1202N 8–pin DIP (IND)NC – No ConnectionDS1202SN 16–pin SOIC (IND)X1, X2 – 32.768 K ..
DS1210 ,Nonvolatile Controller ChipPIN DESCRIPTIONV - RAM SupplyCCOV - + Battery 1BAT1TOL - Power Supply ToleranceGND - GroundCE - Chi ..
DS1210 ,Nonvolatile Controller Chipapplications, data integrity is paramount. In these
DS1210 ,Nonvolatile Controller ChipDS1210Nonvolatile Controller Chip
DS1210 ,Nonvolatile Controller ChipPIN DESCRIPTIONV - RAM SupplyCCOV - + Battery 1BAT1TOL - Power Supply ToleranceGND - GroundCE - Chi ..
DTA114EUA T106 , DTA114E series
DTA114EUA T106 , DTA114E series
DTA114EUAT106 , DTA114E series
DTA114EUA-T106 , DTA114E series
DTA114EUB , PNP -100mA -50V Digital Transistors (Bias Resistor Built-in Transistors)
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DS1202-DS1202N-DS1202S
Serial timekeeping chip
DS1202, DS1202SSerial Timekeeping Chip
DS1202, DS1202S
Copyright 1997 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer toDallas Semiconductor data books.
032697 1/11
FEATURESReal time clock counts seconds, minutes, hours, date
of the month, month, day of the week, and year with
leap year compensation valid up to 210024 x 8 RAM for scratchpad data storageSerial I/O for minimum pin count2.0–5.5 volt full operationUses less than 300 nA at 2 voltsSingle–byte or multiple–byte (burst mode) data trans-
fer for read or write of clock or RAM data8–pin DIP or optional 16–pin SOIC for surface mountSimple 3–wire interfaceTTL–compatible (VCC = 5V)Optional industrial temperature range –40°C to +85°C
(IND)
ORDERING INFORMATIONDS12028–pin DIP
DS1202S16–pin SOIC
DS1202S–88–pin SOIC
DS1202N8–pin DIP (IND)
DS1202SN16–pin SOIC (IND)
DS1202SN–88–pin SOIC (IND)
PIN ASSIGNMENTGND
VCC
SCLK
I/O
RST
16–PIN SOIC
8–PIN DIP
VCC
SCLK
I/O
RST
GND
VCC
SCLK
I/O
RST
GND
8–PIN SOIC(208 mil)
PIN DESCRIPTION–No Connection
X1, X2–32.768 KHz Crystal Input
GND–Ground
RST–Reset
I/O–Data Input/Output
SCLK–Serial Clock
VCC–Power Supply Pin
DESCRIPTIONThe DS1202 Serial Timekeeping Chip contains a real
time clock/calendar and 24 bytes of static RAM. It com-
municates with a microprocessor via a simple serial in-
terface. The real time clock/calendar provides seconds,
minutes, hours, day, date, month, and year information.
The end of the month date is automatically adjusted for
months with less than 31 days, including corrections for
leap year. The clock operates in either the 24–hour or
12–hour format with an AM/PM indicator. Interfacing the
DS1202 with a microprocessor is simplified by using
synchronous serial communication. Only three wires
are required to communicate with the clock/RAM: (1)
RST (Reset), (2) I/O (Data line), and (3) SCLK (Serial
clock). Data can be transferred to and from the clock/
RAM one byte at a time or in a burst of up to 24 bytes.
The DS1202 is designed to operate on very low power
and retain data and clock information on less than 1 mi-
crowatt.
DS1202, DS1202S
032697 2/11
OPERATIONThe main elements of the Serial Timekeeper are shown
in Figure 1: shift register, control logic, oscillator, real
time clock, and RAM. To initiate any transfer of data,
RST is taken high and eight bits are loaded into the shift
register providing both address and command informa-
tion. Data is serially input on the rising edge of the SCLK.
The first eight bits specify which of 32 bytes will be ac-
cessed, whether a read or write cycle will take place,
and whether a byte or burst mode transfer is to occur.
After the first eight clock cycles have occurred which
load the command word into the shift register, additional
clocks will output data for a read or input data for a write.
The number of clock pulses equals eight plus eight for
byte mode or eight plus up to 192 for burst mode.
COMMAND BYTEThe command byte is shown in Figure 2. Each data
transfer is initiated by a command byte. The MSB (Bit 7)
must be a logic 1. If it is zero, further action will be termi-
nated. Bit 6 specifies clock/calendar data if logic 0 or
RAM data if logic 1. Bits one through five specify the
designated registers to be input or output, and the LSB
(Bit 0) specifies a write operation (input) if logic 0 or read
operation (output) if logic 1. The command byte is al-
ways input starting with the LSB (bit 0).
DS1202 BLOCK DIAGRAM Figure 132.768 KHz
I/O
ADDRESS/COMMAND BYTE Figure 26
DS1202, DS1202S
032697 3/11
RESET AND CLOCK CONTROLAll data transfers are initiated by driving the RST input
high. The RST input serves two functions. First, RST
turns on the control logic which allows access to the shift
register for the address/command sequence. Second,
the RST signal provides a method of terminating either
single byte or multiple byte data transfer. A clock cycle is
a sequence of a falling edge followed by a rising edge.
For data inputs, data must be valid during the rising
edge of the clock and data bits are output on t he falling
edge of clock. All data transfer terminates if the RST in-
put is low and the I/O pin goes to a high impedance
state. Data transfer is illustrated in Figure 3.
DATA INPUTFollowing the eight SCLK cycles that input a write com-
mand byte, a data byte is input on the rising edge of the
next eight SCLK cycles. Additional SCLK cycles are ig-
nored should they inadvertently occur. Data is input
starting with bit 0. Due to the inherent nature of the logic
state machine, writing times containing an absolute
value of “59” seconds should be avoided.
DATA OUTPUTFollowing the eight SCLK cycles that input a read com-
mand byte, a data byte is output on the falling edge of
the next eight SCLK cycles. Note that the first data bit to
be transmitted occurs on the first falling edge after the
last bit of the command byte is written. Additional SCLK
cycles retransmit the data bytes should they inadver-
tently occur so long as RST remains high. This opera-
tion permits continuous burst mode read capability.
Data is output starting with bit 0.
BURST MODEBurst mode may be specified for either the clock/calen-
dar or the RAM registers by addressing location 31 deci-
mal (address/command bits one through five = logical
one). As before, bit six specified clock or RAM and bit 0
specifies read or write. There is no data storage capac-
ity at locations 8 through 31 in the Clock/Calendar Reg-
isters or locations 24 through 31 in the RAM registers.
When writing to the clock registers in the burst mode,
the first eight registers must be written in order for the
data to be transferred.
However, when writing to RAM in burst mode it is not
necessary to write all 24 bytes for the data to transfer.
Each byte that is written to will be transferred to RAM
regardless of whether all 24 bytes are written or not.
CLOCK/CALENDARThe clock/calendar is contained in eight write/read reg-
isters as shown in Figure 4. Data contained in the clock/
calendar registers is in binary coded decimal format
(BCD).
CLOCK HALT FLAGBit 7 of the seconds register is defined as the clock halt
flag. When this bit is set to logic 1, the clock oscillator is
stopped and the DS1202 is placed into a low–power
standby mode with a current drain of not more than 100
nanoamps. When this bit is written to logic 0, the clock
will start.
AM–PM/12–24 MODEBit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10 hour bit (20–23 hours).
WRITE PROTECT BITBit 7 of the control register is the write protect bit. The
first seven bits (bits 0–6) are forced to zero and will al-
ways read a zero when read. Before any write operation
to the clock or RAM, bit 7 must be zero. When high, the
write protect bit prevents a write operation to any other
register.
CLOCK/CALENDAR BURST MODEThe clock/calendar command byte specifies burst
mode operation. In this mode the eight clock/calendar
registers can be consecutively read or written (see Fig-
ure 4) starting with bit 0 of address 0.
RAMThe static RAM is 24 x 8 bytes addressed consecutively
in the RAM address space.
RAM BURST MODEThe RAM command byte specifies burst mode opera-
tion. In this mode, the 24 RAM registers can be consec-
utively read or written (see Figure 4) starting with bit 0 of
address 0.
DS1202, DS1202S
032697 4/11
REGISTER SUMMARYA register data format summary is shown in Figure 4.
CRYSTAL SELECTIONA 32.768 KHz crystal, can be directly connected to the
DS1202 via pins 2 and 3 (X1, X2). The crystal selected
for use should have a specified load capacitance (CL) of
6 pF. The crystal is connected directly to the X1 and X2
pins. There is no need for external capacitors or resis-
tors. Note: X1 and X2 are very high impedance nodes.
It is recommended that they and the crystal be guard–
ringed with ground and that high frequency signals be
kept away from the crystal area. For more information
on crystal selection and crystal layout considerations,
please consult Application Note 58, “Crystal Consider-
ations with Dallas Real Time Clocks”.
DATA TRANSFER SUMMARY Figure 3SCLK
I/O
RST23456701234567
ADDRESS COMMANDDATA INPUT/OUTPUT
SINGLE BYTE TRANSFER
SCLK
I/O2345670124567
ADDRESS COMMANDDATA I/O BYTE N
BURST MODE TRANSFER
RST
DATA I/O BYTE 1
DS1202, DS1202S
032697 5/11
REGISTER ADDRESS/DEFINITION Figure 46
REGISTER ADDRESSREGISTER DEFINITION
A. CLOCK
B. RAM
SEC
MIN
DATE
MONTH
DAY
YEAR
CONTROL
CLOCKBURST
01–28/29
RAM 0
RAM 23
RAM
BURST
RAM DATA 0
RAM DATA 23
01–3001–31
DS1202, DS1202S
032697 6/11
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground–0.3V to +7.0V
Operating Temperature0°C to 70°C
Storage Temperature–55°C to +125°C
Soldering Temperature260°C for 10 secondsThis is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 2.0 to 5.5V*)
*Unless otherwise noted.
CAPACITANCE (tA = 25°C)
