DS1110L ,3V 10-Tap Silicon Delay LineApplications♦ TTL/CMOS CompatibleCommunications Equipment♦ Vapor Phase and IR SolderableMedical Dev ..
DS1135 ,3-in-1 High-Speed Silicon Delay LinePIN DESCRIPTION Operation) IN1-IN3 - Input Signals Recommended Replacement for DS1013 OUT1-O ..
DS1135-6 ,3-in-1 High-Speed Silicon Delay LineFEATURES PIN ASSIGNMENT All-silicon timing circuit Three independent buffered delays IN1 ..
DS1135L ,3-Volt 3-in-1 High-Speed Silicon Delay LinePIN DESCRIPTION IN1-IN3 - Input Signals OUT1-OUT3 - Output Signals V - +3V Supply CCGND ..
DS1135L ,3-Volt 3-in-1 High-Speed Silicon Delay LineFEATURES PIN ASSIGNMENT All-Silicon Timing Circuit Three Independent Buffered Delays Sta ..
DS1135LU-10 ,3V 3-in-1 High-Speed Silicon Delay LineFEATURES PIN ASSIGNMENT All-silicon timing circuit Three independent buffered delays Stable and ..
DTA114EK , DTA/DTC SERIES
DTA114EK , DTA/DTC SERIES
DTA114EK , DTA/DTC SERIES
DTA114EM , Built-In Bias Resistors Enable The Configuration of An Inverter Circuit Without Connecting External Input Resistors
DTA114ESATP , Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors
DTA114EUA T106 , DTA114E series
DS1110L
3V 10-Tap Silicon Delay Line
General DescriptionThe DS1110L 10-tap delay line is a 3V version of the
DS1110. It has 10 equally spaced taps providing delays
from 10ns to 500ns. The DS1110L series delay lines
provide a nominal accuracy of ±5% or ±2ns, whichever
is greater, at 3.3V and +25°C. The DS1110L is character-
ized to operate from 2.7V to 3.6V. The DS1110L
produces both leading- and trailing-edge delays with
equal precision. The device is offered in a standard
14-pin TSSOP.
FeaturesAll-Silicon Delay Line3V Version of the DS111010 Taps Equally SpacedDelays Are Stable and PreciseLeading- and Trailing-Edge AccuracyDelay Tolerance ±5% or ±2ns, Whichever Is
Greater, at 3.3V and +25°CEconomicalLow-Profile 14-Pin TSSOPLow-Power CMOSTTL/CMOS CompatibleVapor Phase and IR SolderableFast-Turn PrototypesDelays Specified Over Commercial and Industrial
Temperature RangesCustom Delays Available
DS1110L
3V 10-Tap Silicon Delay LineVCC
TAP1
TAP3
TAP5TAP4
TAP2
N.C.
TOP VIEW
TAP7
TAP9
TAP10GND
TAP8
TAP6
TSSOP (173mil)DS1110L
Pin ConfigurationOrdering InformationXX-XXXX; Rev 1; 11/03
PARTTEM P RANGEPIN-
PACKAGE
TOTAL
DELAYns) *DS1110LE-100-40°C to +85°C14 TSSOP (173mil)100
DS1110LE-125-40°C to +85°C14 TSSOP (173mil)125
DS1110LE-150-40°C to +85°C14 TSSOP (173mil)150
DS1110LE-175-40°C to +85°C14 TSSOP (173mil)175
DS1110LE-200-40°C to +85°C14 TSSOP (173mil)200
DS1110LE-250-40°C to +85°C14 TSSOP (173mil)250
DS1110LE-300-40°C to +85°C14 TSSOP (173mil)300
DS1110LE-350-40°C to +85°C14 TSSOP (173mil)350
DS1110LE-400-40°C to +85°C14 TSSOP (173mil)400
DS1110LE-450-40°C to +85°C14 TSSOP (173mil)450
DS1110LE-500-40°C to +85°C14 TSSOP (173mil)500
*Custom delays are available.
ApplicationsCommunications Equipment
Medical Devices
Automated Test Equipment
PC Peripheral Devices
DS1110L
3V 10-Tap Silicon Delay Line
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(-40°C to +85°C, VCC= 2.7V to 3.6V.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage on Any Pin Relative to Ground.................-0.5V to +6.0V
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...................See IPC/JEDEC J-STD-020A
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply VoltageVCC(Note 1)2.73.33.6V
High-Level Input VoltageVIH(Note 1)2.2VCC
+ 0.3V
Low-Level Input VoltageVIL(Note 1)-0.3+0.8V
Input Leakage CurrentII0V ≤ VI ≤ VCC-1.0+1.0µA
Active CurrentICCVCC = max, period = min (Note 2)40150mA
High-Level Output CurrentIOHVCC = min, VOH = 2.3V-1.0mA
Low-Level Output CurrentIOLVCC = min, VOL = 0.5V12mA
AC ELECTRICAL CHARACTERISTICS(-40°C to +85°C, VCC= 2.7V to 3.6V.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput Pulse WidthtWI(Note 6)10% of
tap 10ns
+25°C, 3.3V (Notes 3, 5, 6, 7, 9)-2Table 1+2
0°C to +70°C (Notes 4–7)-3Table 1+3Input to Tap Delay
(Delays ≤ 40ns)
tPLH
tPHL
-40°C to +85°C (Notes 4–7)-4Table 1+4
+25°C, 3.3V (Notes 3, 5, 6, 7, 9)-5Table 1+5
0°C to +70°C (Notes 4–7)-8Table 1+8Input to Tap Delay
(Delays > 40ns)
tPLH
tPHL
-40°C to +85°C (Notes 4–7)-13Table 1+13
Power-Up TimetPU100ms
Input PeriodPeriod(Note 8)2 (tWI)ns
DS1110L
3V 10-Tap Silicon Delay Line
Note 1:All voltages are referenced to ground.
Note 2:Measured with outputs open.
Note 3:Initial tolerances are ±with respect to the nominal value at +25°C and VCC= 3.3V for both leading and trailing edges.
Note 4:Temperature and voltage tolerances are with respect to the nominal delay value over stated temperature range and a 2.7V to
3.6V range.
Note 5:Intermediate delay values are available on a custom basis.
Note 6:See Test Conditionssection.
Note 7:All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if tap 1 slows down, all other
taps also slow down; tap 3 can never be faster than tap 2.
Note 8:Pulse width and period specifications may be exceeded; however, accuracy is application sensitive (decoupling, layout, etc.).
Note 9:For Tap 1 delays greater than 20ns, the tolerance is ±3ns or ±5%, whichever is greater.
CAPACITANCE(TA= +25°C.)
Typical Operating Characteristics(VCC= 3.3V, TA= +25°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput CapacitanceCIN510pF
CHANGE IN DELAY (%) vs. TEMPERATURE
DS1110L-250DS1110L toc04
TEMPERATURE (°C)
CHANGE IN DELAY (%)3510-15-4085
RISING EDGE
FALLING EDGE
CHANGE IN DELAY (%) vs. TEMPERATURE
DS1110L-500DS1110L toc03
TEMPERATURE (°C)
CHANGE IN DELAY (%)3510-15
RISING EDGE
FALLING EDGE
DELAY CHANGE (%)
vs. VCC DS1110L-250
DS1110L toc02
VCC (V)
CHANGE IN DELAY (%)
RAISING EDGE
FALLING EDGE
DELAY CHANGE (%)
vs. VCC DS1110L-500DS1110L toc01
VCC (V)
CHANGE IN DELAY (%)
RAISING EDGE
FALLING EDGE
DS1110L
3V 10-Tap Silicon Delay Lineypical Operating Characteristics (continued)(VCC= 3.3V, TA= +25°C, unless otherwise noted.)
ACTIVE CURRENT vs. INPUT FREQUENCY
DS1110L-500
DS1110L toc08
FREQUENCY (MHz)
CURRENT (mA)
VCC = 3.6V
15pF LOAD
ON EACH TAP
ACTIVE CURRENT vs. INPUT FREQUENCY
DS1110L-250DS1110L toc07
FREQUENCY (MHz)
CURRENT (mA)1
VCC = 3.6V
15pF LOAD
ON EACH TAP
DS1110L toc06
2.00E-03
4.00E-03
6.00E-03
8.00E-03
1.00E-02
1.20E-02
1.40E-02
1.60E-02
1.80E-02
0.00E+00
OUTPUT CURRENT LOW
vs. OUTPUT VOLTAGE LOW
OUTPUT VOLTAGE LOW (V)
OUTPUT CURRENT LOW (A)
VCC = 2.7V
OUTPUT CURRENT HIGH
vs. OUTPUT VOLTAGE HIGHDS1110L toc05
OUTPUT VOLTAGE HIGH (V)
OUTPUT CURRENT HIGH (A)
-1.60E-02
-1.40E-02
-1.20E-02
-1.00E-02
-8.00E-03
-6.00E-03
-4.00E-03
-2.00E-03
0.00E+0
-1.80E-02
VCC = 2.7V
PINNAMEFUNCTIONINInputN.C.No ConnectionGNDGround
13, 3, 12, 4, 11,
5, 10, 6, 9, 8Tap 1–Tap 10Tap Output NumberVCC2.7V to 3.6V
Pin Description
Detailed DescriptionThe DS1110L 10-tap delay line is a 3V version of
the DS1110. It has 10 equally spaced taps providing
delays from 10ns to 500ns. The device is offered in a
standard 14-pin TSSOP. The DS1110L series delay lines
provide a nominal accuracy of ±5% or ±2ns, whichever is
greater, at 3.3V and +25°C. The DS1110L is character-
ized to operate from 2.7V to 3.6V. The DS1110L repro-
duces the input-logic state at the tap 10 output after a
fixed delay as specified by the dash-number suffix of the
part number (Table 1). The DS1110L produces both lead-
ing- and trailing-edge delays with equal precision. Each
tap is capable of driving up to 10 74LS-type loads. Dallas
Semiconductor can customize standard products to meet
specific needs. Figure 1 is the DS1110_L logic diagram
and Figure 2 shows the timing diagram for the silicon
delay line.
DS1110L
3V 10-Tap Silicon Delay Line10%10%
TAP1TAP2TAP9TAP10
10%10%
Figure 1. Logic Diagram
PARTT O T A L D EL A Y ( n s ) DELAY/TAP (ns)DS1110LE-10010010
DS1110LE-12512512.5
DS1110LE-15015015
DS1110LE-17517517.5
DS1110LE-20020020
DS1110LE-25025025
DS1110LE-30030030
DS1110LE-35035035
DS1110LE-40040040
DS1110LE-45045045
DS1110LE-50050050
Table 1. Part Number by Delay (tPHL, tPLH)VILIN
OUT
0.6V
VIH
tRISE
2.4V
1.5V
1.5V1.5V
1.5V1.5V
0.6V
2.4V
PERIOD
tWI
tPLH
tPLH
tFALL
tWI
DS1110L
Terminology
Period: The time elapsed between the leading edge ofthe first pulse and the leading edge of the following pulse.
tWI(Pulse Width):The elapsed time on the pulse
between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the
trailing edge and the 1.5V point on the leading edge.
tRISE(Input Rise Time):The elapsed time between the
20% and the 80% point on the leading edge of the
input pulse.
tFALL(Input Fall Time): The elapsed time between the80% and the 20% point on the trailing edge of the input
pulse.
tPLH(Time Delay Rising):The elapsed time between
the 1.5V point on the leading edge of the input pulse
and the 1.5V point on the leading edge of any tap out-
put pulse.
tPHL(Time Delay, Falling):The elapsed time between
the 1.5V point on the trailing edge of the input pulse
and the 1.5V point on the trailing edge of any tap out-
put pulse.
Test Setup DescriptionFigure 3illustrates the hardware configuration used for
measuring the timing parameters on the DS1110L. A
precision pulse generator under software control pro-
duces the input waveform. Time delays are measured
by a time interval counter (20ps resolution) connected
3V 10-Tap Silicon Delay LinePULSE
GENERATOR
TIME
INTERVAL
COUNTER
VHF SWITCH
CONTROL UNIT
STOP
DEVICE UNDER TEST
Z0 = 50Ω
START
