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3.3V 5-Tap Economy Timing Element Delay Line
FEATURESAll-Silicon Timing CircuitFive Taps Equally SpacedDelays are Stable and PreciseBoth Leading- and Trailing-Edge Accuracy3.3V Version of the DS1100Low-Power CMOSTTL-/CMOS-compatibleVapor-Phase and IR SolderableCustom Delays AvailableFast-Turn PrototypesDelays Specified Over Both Commercial and
Industrial Temperature Ranges
PIN ASSIGNMENT
PIN DESCRIPTIONTAP 1 to TAP 5- TAP Output Number
VCC- +3.3VGND- Ground- Input
DESCRIPTIONThe DS1100L is a 3.3V version of the DS1100. It is characterized for operation over the range 3.0V to
3.6V. The DS1100L series delay lines have five equally spaced taps providing delays from 4ns to 500ns.These devices are offered in surface-mount packages to save PC board area. Low cost and superior
reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and
industry-standard µSOP and SO packaging. The DS1100L 5-tap silicon delay line reproduces the input-
logic state at the output after a fixed delay as specified by the extension of the part number after the dash.
The DS1100L is designed to reproduce both leading and trailing edges with equal precision. Each tap iscapable of driving up to ten 74LS loads.
Dallas Semiconductor can customize standard products to meet special needs.
DS1100L
3.3V 5-Tap Economy Timing
Element (Delay Line)VCC
TAP 1
TAP 3
TAP 5
TAP 2
TAP 4
GND
DS1100LZ SO (150mil)
DS1100LU µSOP
DS1100L
Figure 1. LOGIC DIAGRAM
Table 1. DS1100L PART NUMBER DELAY TABLE (All Values in ns)
Figure 2. TIMING DIAGRAM: SILICON DELAY LINE
DS1100L
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground-0.5V to +6.0V
Operating Temperature Range-40°C to +85°C
Storage Temperature Range-55°C to +125°C
Soldering TemperatureSee IPC/JEDEC J-STD-020A Specification
Short-Circuit Output Current50mA for 1 second
*This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS(VCC = 3.0V to 3.6V; TA = -40°C to +85°C.)
AC ELECTRICAL CHARACTERISTICS(VCC = 3.0V to 3.6V; TA = -40°C to +85°C.)
CAPACITANCE (TA = +25°C)
DS1100L
NOTES:1) Initial tolerances are ± with respect to the nominal value at +25°C and VCC = 3.3V for both leading
and trailing edge.
2) Temperature and voltage tolerance is with respect to the nominal delay value over the stated
temperature range, and a supply-voltage range of 3.0V to 3.6V.
3) All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP1 slows down, all other taps also slow down; TAP3 can never be faster than TAP2.
4) Intermediate delay values are available on a custom basis. For further information, call (972) 371-
5) All voltages are referenced to ground.
6) Measured with outputs open.7) See Test Conditions section at the end of this data sheet.
8) Frequency higher than 1MHz result in higher ICC values.
9) At or near maximum frequency the delay accuracy can vary and will be application sensitive (i.e.,
decoupling, layout).
Figure 3. TEST CIRCUIT
DS1100L
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leadingedge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of theinput pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of theinput pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the inputpulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the inputpulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTIONFigure 3 illustrates the hardware configuration used for measuring the timing parameters on theDS1100L. The input waveform is produced by a precision pulse generator under software control. Time
delays are measured by a time interval counter (20ps resolution) connected between the input and each
tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements
are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS INPUT:Ambient Temperature:25°C ±3°CSupply Voltage (VCC):3.3V ±0.1V
Input Pulse:High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance:50� maxRise and Fall Time:3.0ns max (measured between 10% and 90%)
Pulse Width:500ns (1µs for -500 version)
Period:1µs (2µs for -500 version)
OUTPUT:Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
DS1100L
ORDERING INFORMATION
