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Partno	Mfg	Dc	Qty	Available	Descript
DS1100-100 |DS1100100	DALLAS	N/a	200	avai	5-Tap Economy Timing Element Delay Line
DS1100-100 |DS1100100	DALLSA	N/a	10	avai	5-Tap Economy Timing Element Delay Line
DS1100-100 |DS1100100	DALLAS ?	N/a	147	avai	5-Tap Economy Timing Element Delay Line
DS1100-100+ |DS1100100	DALLAS	N/a	94	avai	5-Tap Economy Timing Element Delay Line
DS1100-125 |DS1100125	DALLAS	N/a	102	avai	5-Tap Economy Timing Element Delay Line
DS1100-150 |DS1100150	DALLAS	N/a	2	avai	5-Tap Economy Timing Element Delay Line
DS1100-175+ |DS1100175	MAXIM	N/a	13	avai	5-Tap Economy Timing Element Delay Line
DS1100-2.5 |DS110025	DALLAS	N/a	8	avai	5-Tap Economy Timing Element Delay Line
DS1100-20 |DS110020	DALLAS	N/a	251	avai	5-Tap Economy Timing Element Delay Line
DS1100-200 |DS1100200	DALLAS	N/a	30	avai	5-Tap Economy Timing Element Delay Line
DS1100-25 |DS110025		N/a	120	avai	5-Tap Economy Timing Element Delay Line
DS1100-250 |DS1100250	DALLAS ?	N/a	210	avai	5-Tap Economy Timing Element Delay Line
DS1100-250 |DS1100250	DALLAS	N/a	78	avai	5-Tap Economy Timing Element Delay Line
DS1100-30 |DS110030	DS	N/a	97	avai	5-Tap Economy Timing Element Delay Line
DS1100-300 |DS1100300	DALLAS	N/a	134	avai	5-Tap Economy Timing Element Delay Line
DS1100-45 |DS110045	DALLAS	N/a	8	avai	5-Tap Economy Timing Element Delay Line
DS110050	IC	N/a	226	avai	5-Tap Economy Timing Element Delay Line
DS1100-50 |DS110050	DALLAS ?	N/a	687	avai	5-Tap Economy Timing Element Delay Line
DS1100-50+ |DS110050	DALLAS	N/a	30	avai	5-Tap Economy Timing Element Delay Line
DS1100-500 |DS1100500	DALLAS	N/a	121	avai	5-Tap Economy Timing Element Delay Line
DS1100-60 |DS110060	DALLAS	N/a	3	avai	5-Tap Economy Timing Element Delay Line
DS1100-75 |DS110075	DALLAS	N/a	44	avai	5-Tap Economy Timing Element Delay Line
DS1100M-25 |DS1100M25	DALLAS	N/a	241	avai	5-tap economy timing element (delay line), 25ns
DS1100M-50 |DS1100M50		N/a	2676	avai	5-tap economy timing element (delay line), 50ns
DS1100M-75 |DS1100M75	NS	N/a	100	avai	5-tap economy timing element (delay line), 75ns
DS1100Z-100 |DS1100Z100	DALLAS,DALLA	N/a	25000	avai	5-tap economy timing element (delay line), 100ns
DS1100Z-100 |DS1100Z100	DALLAS	N/a	312	avai	5-tap economy timing element (delay line), 100ns
DS1100Z-125 |DS1100Z125	PHILIPS	N/a	295	avai	5-tap economy timing element (delay line), 125ns
DS1100Z-20 |DS1100Z20	MAXIM	N/a	2143	avai	5-tap economy timing element (delay line), 20ns
DS1100Z-35 |DS1100Z35	DALLAS	N/a	580	avai	5-tap economy timing element (delay line), 35ns
DS1100Z-40 |DS1100Z40	DALLAS	N/a	5474	avai	5-tap economy timing element (delay line), 40ns
DS1100Z-50 |DS1100Z50	DALLAS	N/a	1	avai	5-tap economy timing element (delay line), 50ns
DS1100Z-500 |DS1100Z500	DALLAS	N/a	32	avai	5-tap economy timing element (delay line), 500ns
DS1100Z-75 |DS1100Z75	DALLAS	N/a	2487	avai	5-tap economy timing element (delay line), 75ns

DS1100Z-100 ,5-tap economy timing element (delay line), 100nsPIN DESCRIPTIONTAP 1 to TAP 5 - TAP Output NumberV - +5VCCGND - GroundIN - InputDESCRIPTIONThe DS11 ..
DS1100Z-100 ,5-tap economy timing element (delay line), 100nsPIN DESCRIPTIONTAP 1 to TAP 5 - TAP Output NumberV - +5VCCGND - GroundIN - InputDESCRIPTIONThe DS11 ..
DS1100Z-100+ ,5-Tap Economy Timing Element (Delay Line)FEATURES The DS1100 series delay lines have five equally  All-Silicon Timing Circuit spaced taps p ..
DS1100Z-100+T&R ,5-Tap Economy Timing Element (Delay Line)PIN DESCRIPTION TAP 1 to TAP 5 - TAP Output Number V - +5V CCGND - Ground IN - Input µMAX is a ..
DS1100Z-125 ,5-tap economy timing element (delay line), 125nsELECTRICAL CHARACTERISTICS (V = 5.0V ±5%, T = -40°C to +85°C.)CC APARAMETER SYM TEST CONDITION MIN ..
DS1100Z-20 ,5-tap economy timing element (delay line), 20nsELECTRICAL CHARACTERISTICS (V = 5.0V ±5%, T = -40°C to +85°C.)CC APARAMETER SYM TEST CONDITION MIN ..
DTA113ZUA , PNP -100mA -50V Digital Transistors (Bias Resistor Built-in Transistors)
DTA114 EK , DTA/DTC SERIES
DTA114ECA , Built-In Bias Resistors Enable The Configuration of An Inverter Circuit Without Connecting External Input Resistors
DTA114EE ,Pre-biased Transistorsdevice and its external resistor bias network. The Bias ResistorTransistor (BRT) contains a single ..
DTA114EE TL , PNP -100mA -50V Digital Transistors (Bias Resistor Built-in Transistors)
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DS1100-100-DS1100-100+-DS1100-125-DS1100-150-DS1100-175+-DS1100-2.5-DS1100-20-DS1100-200-DS1100-25-DS1100-250-DS1100-30-DS1100-300-DS1100-45-DS110050-DS1100-50-DS1100-50+-DS1100-500-DS1100-60-DS1100-75-DS1100M-25-DS1100M-50-DS1100M-75-DS1100Z-100-DS1100Z-
5-Tap Economy Timing Element Delay Line
FEATURESAll-Silicon Timing CircuitFive Taps Equally Spaced5V OperationDelays are Stable and PreciseBoth Leading- and Trailing-Edge AccuracyImproved Replacement for DS1000Low-Power CMOSTTL/CMOS-CompatibleVapor-Phase, IR, and Wave SolderableCustom Delays AvailableFast-Turn PrototypesDelays Specified Over Both Commercial and
Industrial Temperature Ranges
PIN ASSIGNMENT
PIN DESCRIPTION
TAP 1 to TAP 5- TAP Output Number
VCC- +5VGND- Ground- Input
DESCRIPTION
The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These
devices are offered in 8-pin DIPs and surface-mount packages to save PC board area. Low cost andsuperior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line
and industry-standard DIP and SO packaging. The DS1100 5-tap silicon delay line reproduces the input-
logic state at the output after a fixed delay as specified by the extension of the part number after the dash.
The DS1100 is designed to reproduce both leading and trailing edges with equal precision. Each tap is
capable of driving up to ten 74LS loads.
Dallas Semiconductor can customize standard products to meet special needs.
DS1100
5-Tap Economy Timing
Element (Delay Line)
VCC
TAP 1
TAP 3
TAP 5
TAP 2
TAP 4
GND
DS1100M DIP (300mil)
DS1100Z SO (150mil)DS1100U µSOP
DS1100
Figure 1. LOGIC DIAGRAM
Table 1. DS1100 PART NUMBER DELAY TABLE (All Values in ns)
Figure 2. TIMING DIAGRAM: SILICON DELAY LINE
DS1100
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground-0.5V to +6.0V
Operating Temperature Range-40°C to +85°C
Storage Temperature Range-55°C to +125°C
Soldering TemperatureSee IPC/JEDEC J-STD-020A Specification
Short-Circuit Output Current50mA for 1s
*This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±5%, TA = -40°C to +85°C.)
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±5%, TA = -40°C to +85°C.)
CAPACITANCE (TA = +25°C)
DS1100
NOTES:
1) Initial tolerances are ± with respect to the nominal value at +25°C and 5V for both leading and
trailing edge.
2) Temperature and voltage tolerance is with respect to the nominal delay value over the stated
temperature range, and a supply-voltage range of 4.75V to 5.25V.
3) All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, ifTAP1 slows down, all other taps also slow down; TAP3 can never be faster than TAP2.
4) Intermediate delay values are available on a custom basis. For further information, call
(972) 371-4348.
5) All voltages are referenced to ground.
6) Measured with outputs open.7) See Test Conditions section at the end of this data sheet.
8) Frequencies higher than 1MHz result in higher ICC values.
9) At or near maximum frequency the delay accuracy can vary and will be application sensitive (i.e.,
decoupling, layout).
Figure 3. TEST CIRCUIT
DS1100
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leadingedge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1100.The input waveform is produced by a precision-pulse generator under software control. Time delays are
measured by a time interval counter (20ps resolution) connected between the input and each tap. Each tap
is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS INPUT :
Ambient Temperature:+25°C ±3°CSupply Voltage (VCC):5.0V ±0.1V
Input Pulse:High = 3.0V ±0.1V
Low = 0.0V ±0.1V
Source Impedance:50� maxRise and Fall Time:3.0ns max (measured between 0.6V and 2.4V)
Pulse Width:500ns (1µs for -500 version)
Period:1µs (2µs for -500 version)
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
DS1100
ORDERING INFORMATION
EXAMPLE: The DS1100Z-250 is a 250ns delay (input-to-tap 5) DS1100 in the SO package.

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