DS1085L ,3.3V EconOscillator Frequency SynthesizerPIN DESCRIPTION 2-Wire Serial Interface OUT1 - Main Oscillator Output 0.75% Absolute Accurac ..
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DS1085L
3.3V EconOscillator Frequency Synthesizer
FEATURES User-Programmable Frequency Synthesizer
Programmable From 4.1kHz to 66MHz
Dual Synchronous Outputs
4.13MHz to 66MHz Reference Oscillator
Output
4.1kHz to 66MHz Main Oscillator Output
Single 3.0to3.6V Supply
Three Resolution Options
2-Wire Serial Interface
0.75% Absolute Accuracy
Nonvolatile (NV) Frequency Settings
No External Timing Components
Power-Down Mode
ORDERING INFORMATION
PIN ASSIGNMENT SO (150mil)
PIN DESCRIPTION OUT1 - Main Oscillator Output
OUT0 - Reference Oscillator Output
VCC - Power-Supply Voltage
GND - Ground
CTRL1 - Control Pin for OUT1
CTRL0 - Control Pin for OUT0
SDA - 2-Wire Serial Data Input/Output
SCL - 2-Wire Serial Clock
DEVICE PACKAGE STEP
SIZE
OSCILLATOR
OUTPUT RANGE DS1085LZ-5 150mil SO 5kHz 4.1kHz to 66MHz
DS1085LZ-12 150mil SO 12.5kHz 4.1kHz to 66MHz
DS1085LZ-25 150mil SO 25kHz 4.1kHz to 66MHz
DESCRIPTION The DS1085L is a dual-output frequency synthesizer requiring no external timing components for
operation. It can be used as a standalone oscillator or as a dynamically programmed, processor-controlled
peripheral device. An internal master oscillator can be programmed from 33MHz to 66MHz with three
resolution options of 5kHz, 12.5kHz, and 25kHz. A programmable 3-bit prescaler (divide-by-1, 2, 4, or 8)
permits the generation of a reference oscillator output (OUT0) from the master, ranging from 4.13MHz to
66MHz. A second independent prescaler and a 1-to-1025 divider allow the generation of a main oscillator
output (OUT1) from 4.1kHz to 66MHz. The two outputs, although synchronous with the master, can be
independently programmed. The combination of programmable master oscillator, prescalers, and dividers
allows the generation of thousands of user-specified frequencies. All master oscillator, prescaler, and
divider settings are stored in NV (EEPROM) memory, providing a default value on power-up that allows
it to be used as a standalone oscillator. A 2-wire serial interface allows in-circuit, on-the-fly programming
of the master oscillator, prescalers (P0 and P1), and divider (N). This allows dynamic frequency
modification, if required, or, for fixed-frequency applications, the DS1085L can be used with factory- or
user-programmed values.
DS1085L
3.3V EconOscillator Frequency
Synthesizer
SCL
CTRL0
SDA
CTRL1
OUT1
OUT0
VCC
GND
DS1085L
External control inputs, CTRL1 and CTRL0, enable or disable the two oscillator outputs. Both outputs
feature a synchronous enable that ensures no output glitches when the output is enabled and a constant
time interval (for a given frequency setting) from an enable signal to the first output transition. These
inputs can also be configured to disable the master oscillator, putting the device into a low-power mode
for power-sensitive applications.
Figure 1. DS1085L BLOCK DIAGRAM
OVERVIEW A block diagram of the DS1085L is shown in Figure 1. The DS1085L consists of five major components:
Internal master oscillator (33MHz to 66MHz)
Master oscillator control DAC
Prescalers (divide-by-1, 2, 4, or 8)
Programmable divider (divide-by-1 to 1025)
Control registers
The internal master oscillator provides the reference clock (MCLK), which is fed to the prescalers and
programmable dividers. The frequency of the oscillator can be user-programmed over a two-to-one range
in increments equal to the step size, by means of a 10-bit control DAC. The master oscillator range is
33MHz to 66MHz, which is larger than the range possible with the 10-bit DAC resolution and available
step sizes. Therefore, an additional register (OFFSET) is provided that can be used to select the range of
frequency over which the DAC is used (see Table 1).
0M0 0M1
1M0 1M1
DS1085L
Table 1. DEVICE COMPARISONS BY PART NUMBER
PART NUMBER STEP SIZE (kHz) DAC SPAN (MHz) OFFSET SIZE (MHz) DS1085LZ-5 5 5.12 2.56
DS1085LZ-12 12.5 12.80 3.20
DS1085LZ-25 25 25.60 3.20
For further description of use of the OFFSET register see the REGISTER FUNCTIONS section.
The master clock can be routed directly to the outputs (OUT0 and OUT1) or through separate prescalers
(P0 and P1). In the case of OUT1, an additional programmable divider (N) can be used to generate
frequencies down to 4.1kHz.
The prescaler (P0) divides MCLK by 1, 2, 4, or 8 before routing MCLK to the reference output (OUT0)
pin.
The prescaler (P1) divides MCLK by 1, 2, 4, or 8 before routing MCLK to the programmable divider (N),
and ultimately to the main output (OUT1) pin.
The programmable divider (N) divides the prescaler output (P1) by any number selected between two and
1025 (10 bits) to provide the main output (OUT1), or it can be bypassed altogether by use of the DIV1
register bit. The value of N is stored in the DIV register.
The control registers are user-programmable through a 2-wire serial interface to determine operating
frequency (values of DAC, OFFSET, P0, P1, and N) and modes of operation. Once programmed, the
register settings are nonvolatile and only need reprogramming if it is desired to reconfigure the device.
PIN DESCRIPTIONS
PIN NAME FUNCTION 1 OUT1
This main oscillator output frequency is determined by the control
register settings for the oscillator (DAC and OFFSET), prescaler P1
(mode bits 1M0 and 1M1), and divider N (DIV).
2 OUT0
The reference output is taken from the output of the reference select mux.
Its frequency is determined by the control register settings for prescaler
P0 (mode bits 0M0 and 0M1) (see Table 2).
3 Vcc Power Supply
4 GND Ground
5 CTRL0
A multifunction control input pin that can be programmed to function as
a mux select, ouput enable, and/or a power-down. Its function is
determined by the user-programmable control register values of EN0,
SEL0, and PDN0 (see Table 2).
6 CTRL1
A multifunction control input pin that can be programmed to function as
an output enable and/or a power-down. Its function is determined by the
user-programmable control register value of PDN1 (see Table 3). SDA I/O pin for the 2-wire serial interface used for data transfer.
8 SCL Input pin for the 2-wire serial interface used to synchronize data
movement over the serial interface.
DS1085L
Table 2. DEVICE MODE USING OUT0
EN0
(BIT)
SEL0
(BIT)
PDN0
(BIT)
CTRL0
(PIN)
OUT0
(PIN)
CTRL0
FUNCTION
DEVICE
MODE 1 High-Z Power-Down*** 0 0 0 0 High-Z
Power-Down*
Active
1 MCLK/M 0 1 0 0 MCLK
Mux Select Active
1 High-Z 1 0 0 0 MCLK
Output Enable Active
1 High-Z 1 1 0 0 MCLK/M
Output Enable Active**
1 High-Z Power-Down X 0 1 0 MCLK
Power-Down
Active
1 High-Z Power-Down X 1 1 0 MCLK/M
Power-Down
Active
* This mode is for applications where OUT0 is not used, but CTRL0 is used as a device shutdown.
** Factory default setting.
***See standby (power-down) current specification for power-down current range.
Table 3. DEVICE MODE USING OUT1
PDN1
(BIT)
CTRL1
(PIN)
CTRL1
FUNCTION OUT1 (PIN) DEVICE MODE 0 0 OUT CLK
0 1 Output Enable High-Z Active*
1 0 OUT CLK Active
1 1 Power-Down High-Z Power-Down
*Factory default setting
NOTE: Both CTRL0 and CTRL1 can be configured as power-downs. They are internally “OR” connected so
either of the control pins can be used to provide a power-down function for the whole device, subject to
appropriate settings of the PDN0 and PDN1 register bits (see Table 4).
Table 4. SHUTDOWN CONTROL WITH PDN0 AND PDN1
PDN0
(BIT)
PDN1
(BIT) SHUTDOWN CONTROL 0 0 NONE
0 1 CTRL1
1 0 CTRL0 1 CTRL1 OR CTRL0
DS1085L
REGISTER FUNCTIONS The user-programmable registers can be used to determine the mode of operation (MUX), operating
frequency (DAC, OFFSET, DIV), and bus settings (ADDR). The functions of the registers are described
in this section, but the details of how these registers are programmed can be found in a later section. The
register settings are nonvolatile, with the values being stored automatically or as required in EEPROM
when the registers are programmed through the SDA and SCL pins.
DAC WORD (Address 08h) MSB LSB MSB LSB
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 X X X X X X
First Data Byte Second Data Byte
X = Don’t care.
The DAC word (d0–d9) controls the frequency of the master oscillator. The resolution of this register
depends on the step size of the device. The absolute frequency of the device also depends on the value of
the OFFSET register (see Tables 5 and 6).
Table 5. DEVICE DEFAULT SETTINGS
DS1085LZ-5 DS1085LZ-12 DS1085LZ-25
Frequency DAC Offset Frequency DAC Offset Frequency DAC Offset 48.58MHz 500 OS 52.3MHz 600 OS 50.9MHz 500 OS
For any given value of OFFSET the master oscillator frequency can be derived as follows:
Frequency = Min Frequency + DAC x Step Size
where: Min frequency is the lowest frequency shown in Table 6 for the corresponding offset.
DAC is the value of the DAC register (0–1023).
Step size is the step size of the device (5kHz, 12.5kHz, or 25kHz).
OS is the decimal, integer value of the 5 MSBs of the RANGE register.
OFFSET BYTE (Address 0Eh)
MSB LSB
X X X O4 O3 O2 O1 O0
X = Don’t care.
The OFFSET byte (O0–O4) determines the range of frequencies that can be obtained within the absolute
minimum and maximum range of the oscillator. Correct operation of the device is not guaranteed for
values of OFFSET not shown in Table 6.
DS1085L
Table 6. FREQUENCY vs. OFFSET
DS1085LZ-5 DS1085LZ-12 DS1085LZ-25
OFFSET FREQUENCY
RANGE
FREQUENCY
RANGE
FREQUENCY
RANGE OS - 10 — — —
OS - 9 — — —
OS - 8 — — —
OS - 7 — — —
OS - 6 30.7 to 35.8 25.6 to 38.4 19.2 to 44.8
OS - 5 33.3 to 38.4 28.8 to 41.6 22.4 to 48.0
OS - 4 35.8 to 41.0 32.0 to 44.8 25.6 to 51.2
OS - 3 38.4 to 43.5 35.2 to 48.0 28.8 to 54.4
OS - 2 41.0 to 46.1 38.4 to 51.2 32.0 to 57.6
OS - 1 43.5 to 48.6 41.6 to 54.4 35.2 to 60.8
OS* 46.1 to 51.2 44.8 to 57.6 38.4 to 64.0
OS + 1 48.6 to 53.8 48.0 to 60.8 41.6 to 67.2
OS + 2 51.2 to 56.3 51.2 to 64.0 44.8 to 70.4
OS + 3 53.8 to 58.9 54.4 to 67.2 48.0 to 73.6
OS + 4 56.3 to 61.4 57.6 to 70.4 51.2 to 76.8
OS + 5 58.9 to 64.0 60.8 to 73.6 54.4 to 80.0
OS + 6 61.4 to 66.6 64.0 to 76.8 57.6 to 83.2
*OS is the OFFSET default setting. OS is the integer value of the five MSBs of RANGE register.
These ranges include values outside the oscillator range of 33MHz to 66MHz. When using these ranges,
values of DAC must be chosen to keep the oscillator within range. Correct operation of the device is not
guaranteed outside the range 33MHz to 66MHz.
MUX WORD (Address 02h) The MUX word controls several functions. Its bits are organized as follows:
MSB LSB MSB LSB
NAME * PDN1 PDN0 SEL0 EN0 0M1 0M0 1M1 1M0 DIV1 – – –––– Default
Setting 0 0 0 1 1 0 0 0 0 0 X X XXXX
* This bit must be set to zero.
X = Don’t care.
DS1085L
The functions of the individual bits are described in the following paragraphs.
DIV1 (Default Setting = 0)
This bit allows the output of the prescaler P1 to be routed directly to the
OUT1 pin (DIV1 = 1). In this condition, the N divider is bypassed so the
programmed value of N is ignored. If DIV1 = 0, the N divider functions
normally.
EN0 (Default Setting = 1) If EN0 = 1 and PDN0 = 0, the CTRL0 functions as an output enable for OUT0, the frequency of the
output being determined by the SEL0 bit.
If PDN0 = 1, the EN0 bit is ignored, CTRL0 functions as a power-down, and OUT0 is always enabled on
power-up, its frequency determined by the SEL0 bit.
If EN0 = 0, the function of CTRL0 is determined by the SEL0 and PDN0 bits (see Table 2).
SEL0 (Default Setting = 1) If SEL0 = 1 and EN0 = PDN0 = 0, the CTRL0 pin determines whether the prescaler is bypassed,
controlling the output frequency.
If CTRL0 = 0, the output frequency equals MCLK.
If CTRL0 = 1, the output frequency equals MCLK/M.
If either EN0 or PDN0 = 1, the CTRL0 pin functions as an output enable or power-down and the SEL0
bit determines whether the prescaler is bypassed, thus controlling the output frequency.
If SEL0 = 0, the output is MCLK, the master clock frequency.
If SEL0 = 1, the output is the output frequency of the M prescaler (see Table 2).
PDN0 (Default Setting = 0) If PDN0 = 1, the CTRL0 performs a power-down function, regardless of the setting of the other bits.
If PDN0 = 0, the function of CTRL0 is determined by the values of EN0 and SEL0 (see Table 2).
0M0, 0M1, 1M0, 1M1 (Default Setting = 0) These bits set the prescaler’s (P0 and P1) divisor (M) to 1, 2, 4, or 8 (see Table 7a and 7b).
DS1085L
Table 7a. PRESCALER P0 DIVISOR M SETTINGS
0M1 0M0 PRESCALER P0
DIVISOR “M” 0 0 1*
0 1 2
1 0 4
1 1 8
*Factory Default Setting
Table 7b. PRESCALER P1 DIVISOR M SETTINGS
1M1 1M0 PRESCALER P1
DIVISOR “M” 0 0 1*
0 1 2
1 0 4
1 1 8
*Factory Default Setting
NOTE: When EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down. This is a special case for
situations when OUT0 is not used. Under these conditions all the circuitry associated with OUT0 is
powered down. OUT0 is powered down (see Table 2).
PDN1 (Default Setting = 0) If PDN1 = 1, CTRL1 functions as a power-down (see Table 3). If PDN1 = 0, CTRL1 functions as an output enable for OUT1 (see Table 3).
NOTES FOR OUTPUT ENABLE AND POWER-DOWN: 1) Both enables are “smart” and wait for the output to be low before going High-Z.
2) A power-down sequence first disables both outputs before powering down the device.
3) On power-up, the outputs are disabled until the clock has stabilized (~8000 cycles).
4) In power-down mode the device cannot be programmed.
5) A power-down command must persist for at least two cycles of the lowest output frequency plus
10µs.
DIV WORD (N) (Address 01h) MSB LSB MSB LSB
N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 X X X X X X
First Data Byte Second Data Byte
X = Don’t care.
DS1085L
The DIV word sets the programmable divider. These 10 bits (N0–N9) determine the value of the
programmable divider (N). The range of divisor values is from two to 1025, and is equal to the
programmed value of N plus 2 (see Table 8).
Table 8. PROGRAMMABLE DIVISOR N VALUES
BIT VALUE DIVISOR (N) 00000000 00XXXXXX 2*
00000000 01XXXXXX 3
— —
— —
— —
— —
11111111 11XXXXXX 1025
* Factory Default Setting
ADDR BYTE (Address 0Dh) MSB LSB
NAME — — — — WC A2 A1 A0 Factory
Default
X X X X 0 0 0
X = Don’t care.
A0, A1, A2 (Default Setting = 000) These device select bits determine the 2-wire address of the device.
WC (Default Setting = 0) This bit determines when/if the EEPROM is written to after register contents have been changed. If
WC = 0, EEPROM is written automatically after a write register command. If WC = 1, EEPROM is only
written when the “WRITE” command is issued. In applications where the register contents are frequently
rewritten, WC should be set to 1; otherwise, it is necessary to wait for an EEPROM write cycle to
complete (up to 10ms) between writing to the registers. Regardless of the value of the WC bit, when the
ADDR register (A0, A1, A2) is written, the current value in all registers (DAC, OFFSET, DIV, MUX,
and ADDR) are immediately to the EEPROM.
RANGE REGISTER (Address 37h) MSB LSB
OS5 OS4 OS3 OS2 OS1 X X X X X X X X X X X
The first five bits of the RANGE register contain the default OFFSET value. The decimal value of the
RANGE register is the value OS that is referred to in Table 6. The RANGE register is read-only.
DS1085L
COMMAND SET Data and control information is read from and written to the DS1085L in the format shown in Figure 3.
To write to the DS1085L, the master issues the slave address of the DS1085L and the R/W bit is set to 0.
After receiving an acknowledge, the bus master provides a command protocol. After receiving this
protocol, the DS1085L issues an acknowledge, and then the master can send data to the DS1085L. If the
DS1085L is to be read, the master must send the command protocol as before, and then issue a repeat
START condition and then the control byte again, this time with the R/W bit set to 1 to allow reading of
the data from the DS1085L. The command set for the DS1085L is listed as follows:
Access DAC [08h] If R/W is 0, this command writes to the DAC register. After issuing this command, the next data byte
values are written into the DAC register. If R/W is 1, the next data bytes read are the values stored in the
DAC register. This is a 2-byte transfer, the first byte contains the eight MSBs, and the second byte
contains the two LSBs in the most significant positions of the data byte. The remaining six bits are
ignored and can be written with any value (if read, these bits are 0).
Access OFFSET [0Eh] If R/W is 0, this command writes to the OFFSET register. After issuing this command, the next data byte
value is written into the OFFSET register. If R/W is 1, the next data byte read is the value stored in the
OFFSET register. This is a single-byte transfer of which only the five LSBs (last five bits) are used. The
remaining three bits can be written with any value to complete the data byte (if read, these bits are 1).
Access DIV [01h] If R/W is 0, this command writes to the DIV register. After issuing this command, the next data byte
values are written into the DIV register. If R/W is 1, the next data bytes read are the values stored in the
DIV register. This register has a 10-bit value. The upper eight bits are sent first, followed by a second
byte that contains the two LSBs of the register value in the most significant positions of the data byte.
The remaining six bits are ignored and can be set to any value (if read, these bits are 0).
Access MUX [02h] If R/Wis 0, this command writes to the MUX register. After issuing this command, the next data byte
values are written into the MUX register. If R/W is 1, the next data bytes read are the values stored in the
MUX register. This register has a 10-bit value. The upper eight bits are sent first, followed by a second
byte that contains the two LSBs of the register value in the most significant positions of the data byte.
The remaining six bits are ignored and can be set to any value (if read, these bits are 0).
Access ADDR [0Dh] If R/W is 0, this command writes to the ADDR register. After issuing this command, the next data byte
value is written into the ADDR register. If R/W is 1, the next data byte read is the value stored in the
ADDR register. This is a single-byte transfer. This register has a 5-bit value, the first three bits of a write
can be any value followed by the five active bits (if read, the first three bits are 0).
DS1085L
Access RANGE [37h] If R/W is 1, the next data bytes read are the values stored in the RANGE register. This register has a 14-
bit value. The upper eight bits are sent first, followed by a second byte that contains the five LSBs of the
register value in the most significant positions of the data byte. The upper five MSB’s of the first byte
contain the OS value for the frequency adjust Table 6. The register is read-only.
Write E2 [3Fh] If WC = 0, the EEPROM is automatically written to at the end of each write command. This is a
DEFAULT condition. In this case the command “WRITE E2” is not needed. If WC = 1, the EEPROM is
written when the “WRITE E2” command is issued. On receipt of the “WRITE E2” command, the
contents of the DAC, OFFSET, ADDR, DIV and MUX registers are written into the EEPROM, thus
locking in the register settings.
EXCEPTION: The DAC, OFFSET, ADDR, DIV, and MUX registers are always automatically written to
EEPROM after a write to the ADDR register regardless of the value of the WC bit.
