DS1075 Fast Delivery |IC PHOENIX CO.,LIMITED

DS1075 ,EconOscillator/Dividerfeatures a master oscillator followed by a prescaler and then a programmable divider. Theprescaler ..
DS1075 ,EconOscillator/DividerFEATURES PIN ASSIGNMENT Dual Fixed frequency outputs1 8I/O OSCIN(30 KHz - 100 MHz)OUT0 2 7 XTAL U ..
DS1075M-100 ,EconOscillator/divider, max 100MHzPIN DESCRIPTIONSInput/Output Pin (IN/OUT): This pin is the main oscillator output, with a frequency ..
DS1075Z-100 ,EconOscillator/divider, max 100MHzDS1075EconOscillator/Divider.com
DS1075Z-100+ ,EconOscillator/DividerBLOCK DIAGRAM Figure 1PART INTOSCNO. FREQUENCYSUFFIX-100 100.000 MHz080 80.000 MHz-66 66.667 MHz-60 ..
DS1075Z-60 ,EconOscillator/divider, max 60MHzfeatures a master oscillator followed by a prescaler and then a programmable divider. Theprescaler ..
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DS1075
EconOscillator/Divider
FEATURESDual Fixed frequency outputs
(30 KHz - 100 MHz)User-programmable on-chip dividers
(from 1 - 513)User-programmable on-chip prescaler
(1, 2, 4)No external components0.5% Initial tolerance1% variation over temperature and voltageInternal clock, External clock or crystal
reference optionsSingle 5V supplyPower-down modeSynchronous output gating
PIN ASSIGNMENT
FREQUENCY OPTIONS
Part No. Max O/P freq.
DS1075-100 100.000 MHz
DS1075-80 80.000 MHz
DS1075-66 66.667 MHz
DS1075-60 60.000 MHz
DESCRIPTION
The DS1075 is a fixed frequency oscillator requiring no external components for operation. Numerous
operating frequencies are possible in the range of approximately 30 KHz to 100 MHz through the use of
an on-chip programmable prescaler and divider.
The DS1075 features a master oscillator followed by a prescaler and then a programmable divider. The
prescaler and programmable divider are user-programmable with the desired values being stored in
nonvolatile memory. This allows the user to buy an off the shelf component and program it on site prior
to board production. Design changes can be readily accommodated by programming, or reprogramming,
the desired values into the on-chip nonvolatile registers. Evaluation boards, DS1075K and DS1070K are
available to simplify this task.
The DS1075 is shipped from the factory configured for half the maximum operating frequency. Contact
the factory for specially programmed devices. As alternatives to the on-board oscillator an external clock
signal or a crystal may be used as a reference. The choice of reference source (internal or external) is
user-selectable at the time of programming (or on the fly if the SEL mode is chosen).
The DS1075 features a dual-purpose Input/Output pin. If the device is powered up in Program mode this
pin can be used to input serial data to the on-chip registers. After a Write command this data is stored in
nonvolatile memory. When the chip is subsequently powered up in operating mode these values are
automatically restored to the on-chip registers and the Input/Output pin becomes the oscillator output.
The DS1075 is available in 8-pin DIP or SOIC packages, allowing the generation of a clock signal easily,
DS1075
EconOscillator/Divider
.com
I/O
OUT0
VCC
GND
OSCIN
PDN/SELX
XTAL
DS1075Z 150-MIL SOIC
DS1075M 300-MIL DIP
DS1075
BLOCK DIAGRAM Figure 1
PART
NO.
SUFFIX
INTOSC
FREQUENCY
100.000 MHz
80.000 MHz
66.667 MHz
60.000 MHz
DS1075
PIN DESCRIPTIONS
Input/Output Pin (IN/OUT): This pin is the main oscillator output, with a frequency determined by clock
reference, M and N dividers. Except in programming mode this pin is always an output and will be
referred to as “OUT”. In programming mode this pin will be referred to as “IN”.
External Oscillator Input (OSCIN): This pin can be used to supply an external reference frequency to
the device.
Crystal Oscillator Connection (XTAL): A crystal can be connected between this pin and OSCIN to
provide an alternative frequency reference. If a crystal is not used this pin should be left open.
Output Enable Function (OE pin): The DS1075 also features a “synchronous” output enable. When
OE is at a high logic level the oscillator free runs. When this pin is taken low OUT is held low,
immediately if OUT is already low, or at it’s next high-to-low transition if OUT is high. This prevents
any possible truncation of the output pulse width when the enable is used. While the output is disabled
the master oscillator continues to run (producing an output at OUT0, if the EN0 bit = 0) but the internal
counters (/N) are reset. This results in a constant phase relationship between OE’s return to a high level
and the resulting OUT signal. When the enable is released OUT will make its first transition within one
to two clock periods of the master clock.
Power-Down/Select Function (PDN/SELXPDN/SELX pin): The Power-Down/Select (PDN/SELX) pin
has a user-selectable function determined by one bit (PDN bit) of the user-programmable memory.
According to which function is selected, this pin will be referred to as PDN or SELX.
If the Power-Down function is selected (PDN bit = 1) a low logic level on this pin can be used to make
the device stop oscillating (active low) and go into a reduced power consumption state. The “Enabling
Sequencer” circuitry will first disable OUT in the same way as when OE is used. Next OUT0 will be
disabled in a similar fashion. Finally the oscillator circuitry will be disabled. In this mode both outputs
will go into a high impedance state. The power consumption in the power-down state is much less than if
OE is used because the internal oscillator (if used) is completely powered down. Even if an external
reference or a crystal is used all of the on-chip buffers are powered down to minimize current drain.
Consequently the device will take considerably longer to recover (i.e., achieve stable oscillation) from a
power-down condition than if the OE is used.
If the Select function is chosen (PDN bit = 0) this pin can be used to switch between the internal
oscillator and an external reference (or crystal) on the fly. When this mode is chosen the E/I select bit is
overridden, a high logic level on SELX will select the internal oscillator, a low logic level will select the
external reference (or crystal oscillator).
Reference Output (OUT0 pin): A reference output, OUT0, is also available from the output of the
reference select mux. This output is especially useful as a buffered output of a crystal defined master
frequency. OUT0 is unaffected by the OE pin, but is disabled in a glitchless fashion if the device is
powered down. If this output is not required it can be permanently disabled by setting the EN0 bit to one,
and there will be a corresponding reduction in overall power consumption.
USER-PROGRAMMABLE REGISTERS
The following registers can be programmed by the user to determine operating frequency and mode of
DS1075
the function of the registers are described. The register settings are nonvolatile, the values being stored
automatically in EEPROM when the registers are programmed.
Note: The register bits cannot be used to make mode or frequency changes on the fly. Changes can only
be made by powering the device up in “Programming” mode. For them to be become effective the device
must then be powered down and powered up again in “Operation” mode.
For programming purposes the register bits are divided into two 9-bit words, the “MUX” word
determines mode of operation and prescaler values. The “DIV” word sets the value of the programmable
divider.
MUX WORD Figure 2
(MSB)(LSB)0*0*EN0PDNMMSELDIV1E/I
* These bits must be set to zero
E/I
This bit selects either the internal oscillator or the external/ crystal reference.
1=External/Crystal
0=Internal Oscillator
however, if the PDN bit is set to zero the E/I bit will be overridden by the logic level on the
PDN/SELXpin.
Table 1
PDN
BITE/I
PDN/SELX
PIN
OSCILLATOR
MODEX0EXTERNAL/CRYSTALX1INTERNALX0POWER-DOWN01INTERNAL11EXTERNAL/CRYSTAL
DIV1
This bit allows the master clock to be routed directly to the output (DIV1=1). The N programmable
divider is bypassed so the programmed value of N is ignored. The frequency of the output (fOUT) will be
INTCLK or EXTCLK depending on which reference has been selected. If the Internal clock is selected
the M prescaler is also bypassed (the bit values of MSEL and M are ignored) so in this case fOUT
=INTOSC (which also equals MCLK and INTCLK). If DIV1=0 the prescaler and programmable divider
function normally.
MSEL
This bit determines whether or not the M prescaler is bypassed. MSEL=1 will bypass the prescaler.
MSEL=0 will switch in the prescaler (unless overridden by DIV1=1), with a divide-by number
determined by the M bit.
This bit sets the divide-by number for the prescaler. M=0 results in divide-by-4, M=1 results in divide-
DS1075
Table 2
DIV1
BIT
E/I
BIT*
MSEL
BIT
BITOPERATION
0000INTERNAL OSCILLATOR DIVIDED BY 4*N
0001INTERNAL OSCILLATOR DIVIDED BY 2*N01XINTERNAL OSCILLATOR DIVIDED BY N1XXEXTERNAL OSCILLATOR DIVIDED BY N0XXINTERNAL OSCILLATOR DIVIDED BY 11XXEXTERNAL OSCILLATOR DIVIDED BY 1
*Assuming PDN bit = 1, otherwise internal/external selection will be controlled by the PDN/SELX pin.
DIV WORD Figure 3
(MSB)(LSB)
N (9-BITS)
PDN
This bit is used to determine the function of the PDN/SELX pin. If PDN=0, the PDN/SELX pin can be
used to determine the timing reference (either the internal oscillator or an external reference/crystal). If
PDN=1, the PDN/SELX pin is used to put the device into power-down mode.
EN0
This bit is used to determine whether the OUT0 pin is active or not. If EN0 =1, OUT0 is disabled (High-
impedance). If EN0=0, the internal reference clock (MCLK) is output from OUT0. The OE pin has no
effect on OUT0, but OUT0 is disabled as part of the power-down sequence.
These nine bits determine the value of the programmable divider. The range of divisor values is from 2 to
513, and is equal to the programmed value of N plus 2:
Table 3
BIT
VALUES
DIVISOR (N)
VALUE
NOTE:
The maximum value of N is constrained by the minimum output frequency. If the internal clock is
selected, INTOSC/(M*N) must be greater than fOUTmin; if the external clock is selected, EXTCLK/N must
be greater than fOUTmin . (If DIV1=1, then INTOSC or EXTCLK, as applicable, must exceed fOUTmin).
DS1075
OPERATION OF OUTPUT ENABLE
Since the output enable, internal master oscillator and/or external master oscillator are likely all
asynchronous there is the possibility of timing difficulties in the application. To minimize these
difficulties the DS1075 features an “enabling sequencer” to produce predictable results when the device is
enabled and disabled. In particular the output gating is configured so that truncated output pulses can
never be produced.
ENABLE TIMING
The output enable function is produced by sampling the OE input with the output from the prescaler mux
(MCLK) and gating this with the output from the programmable divider. The exact behavior of the
device is therefore dependent on the setup time (tSU) from a transition on the OE input to the rising edge
of MCLK. If the actual setup time is less than tSUEM then one more complete cycle of MCLK will be
required to complete the enable or disable operation (see diagrams). This is unlikely to be of any
consequence in most applications, and then only if the value for N is small. In general, the output will
make its first positive transition between approximately one and two clock periods of MCLK after the
rising edge of OE.
FIGURE 4

DISABLE TIMING
If OE goes low while OUT is high, the output will be disabled on the completion of the output pulse. If
OUT is low, the disabling behavior will be dependent on the setup time between the falling edge of OE
and the rising edge of MCLK. If tSU < tSUEM the result will be one additional pulse appearing on the
output before disabling occurs. If the device is in divide-by-one mode, the disabling occurs slightly
differently. In this case if tSU > tSUEM one additional output pulse will appear, if tSU < tSUEM then two
additional output pulses will appear.
The following diagrams illustrate the timing in each of these cases.
DS1075
Figure 5

Figure 6

SELECT TIMING
If the PDN bit is set to “0”, the PDN/SELX pin can be used to switch between the internal oscillator and
an externalor crystal reference. The “Enabling Sequencer” is again employed to ensure this transition
occurs in a glitch-free fashion. Two asynchronous clock signals are involved, INTCLK is the internal
reference oscillator divided by one or whatever value of M is selected. EXTCLK is the clock signal fed
into the OSCIN pin, or the clock resulting from a crystal connected between OSCIN and XTAL. The
behavior of OUT0 is described in the following paragraphs, the OUT pin will behavior similarly but will
be divided by N.
FROM INTERNAL TO EXTERNAL CLOCK
This is accomplished by a high to low transition on the SELX pin. This transaction is detected on the
falling edge of INTCLK. The output OUT0 will be held low for a minimum of half the period of
INTCLK (tI/2), then if EXTCLK is low it will be routed through to OUT0. If EXTCLK is high the
switching will not occur until EXTCLK returns to a low level.
DS1075
Figure 7

Depending on the relative timing of the SELX signal and the internal clock, there may be up to one full
cycle of tI on the output after the falling edge of SELX. Then, the “low” time (tLOW) between output
pulses will be dependent on the relative timing between tI and tE. The time interval between the falling
edge of SELX and the first rising edge of the externally derived clock is tSIE. Approximate maximum and
minimum values of these parameters are:
tLOW (min) = tI/2
tLOW (max) = tI/2 + tE
tSIE (min) = tI/2
tSIE (max) = 3 tI/2 + tE
NOTE:
In each case there will be a small additional delay due to internal propagation delays.
FROM EXTERNAL TO INTERNAL CLOCK
This is accomplished by a low to high transition on the SELX pin. In this case the switch is level
triggered, to allow for the possibility of a clock signal not being present at OSCIN. Note therefore, that if
a constant high-level signal is applied to OSCIN it will not be possible to switch over to the internal
reference. (Level triggering was not employed for the switch from internal to external reference as this
approach is slower and the internal clock may be running at a much higher frequency than the maximum
allowed external clock rate). When SELX is high and a low level is sensed on EXTCLK, OUT0 will be
held low until a falling edge occurs on INTCLK, then the next rising edge of INTCLK will be routed
through to OUT0.
Figure 8

Depending on the relative timing of the SELX signal and the external clock, there may be up to one full tE
DS1075
edge of SELX and the first rising edge of the externally derived clock is t SIE . Approximate maximum
and minimum values of these parameters are:
tLOW (min) = tI/2
tLOW (max) = 3tI/2 + tElow
tSIE (min) = tI/2
tSIE (max) = 3 tI/2 + tEhigh
NOTE:
In each case there will be a small additional delay due to internal propagation delays.
POWER-DOWN CONTROL
If the PDN bit is set to “1”, the PDN/SELX pin can be used to power-down the device. If PDN is high
the device will run normally.
POWER-DOWN
If PDN is taken low a power-down sequence is initiated. The “Enabling Sequencer” is used to execute
events in the following sequence:
1. Disable OUT (same sequence as when OE is used) and reset N counters.
2. When OUT is low, switch OUT to high-impedance state.
3. Disable MCLK (and OUT0 if EN0 bit = 0), switch OUT0 to high impedance state.
4. Disable internal oscillator and OSCIN buffer.
POWER-UP
When PDN is taken to a high level the following power-up sequence occurs:
1. Enable internal oscillator and/or OSCIN buffer.
2. Set M and N to maximum values.
3. Wait approximately 256 cycles of MCLK for it to stabilize.
4. Reset M and N to programmed values.
5. Enable OUT0 (assuming EN0 bit = 0).
6. Enable OUT.
Steps 2 through 4 exist to allow the oscillator to stabilize before enabling the outputs.

Partno	Mfg	Dc	Qty	Available	Descript
DS1075	MAXIM	N/a	134	avai	EconOscillator/Divider
DS1075	DS	N/a	11	avai	EconOscillator/Divider