DS1073Z-100 ,3V EconOscillator/divider, max 100MHzFEATURES PIN ASSIGNMENT Dual fixed-frequency outputs (30kHz to100MHz) 1 8I/O OSCIN User-programma ..
DS1073Z-100. ,3V EconOscillator/divider, max 100MHzfeatures a master oscillator followed by a prescaler and then a programmable divider. Theprescaler ..
DS1075 ,EconOscillator/Dividerfeatures a master oscillator followed by a prescaler and then a programmable divider. Theprescaler ..
DS1075 ,EconOscillator/DividerFEATURES PIN ASSIGNMENT Dual Fixed frequency outputs1 8I/O OSCIN(30 KHz - 100 MHz)OUT0 2 7 XTAL U ..
DS1075M-100 ,EconOscillator/divider, max 100MHzPIN DESCRIPTIONSInput/Output Pin (IN/OUT): This pin is the main oscillator output, with a frequency ..
DS1075Z-100 ,EconOscillator/divider, max 100MHzDS1075EconOscillator/Divider.com
DT5A124E , Transistor Switch Digital Transistor Arrays (Inclusdes Resistors)
DT5A124E , Transistor Switch Digital Transistor Arrays (Inclusdes Resistors)
DT5A143E , Transistor Switch Digital Transistor Arrays (Inclusdes Resistors)
DT5A143E , Transistor Switch Digital Transistor Arrays (Inclusdes Resistors)
DT5C114E , Transistor Switch Digital Transistor Arrays (Inclusdes Resistors)
DT5C124E , Transistor Switch Digital Transistor Arrays (Inclusdes Resistors)
DS1073Z-100-DS1073Z-100.
3V EconOscillator/divider, max 100MHz
FEATURESDual fixed-frequency outputs (30kHz to
100MHz)User-programmable on-chip dividers (from 1to 513)User-programmable on-chip prescaler (1, 2,No external components�0.5% initial tolerance (commercial)�1% variation over commercial temperature
and voltageInternal clock, external clock or crystal
reference options2.7 to 3.6V supplyPower-down modeSynchronous output gatingIndustrial temp operation with relaxed
specifications
PIN ASSIGNMENT
FREQUENCY OPTIONS
Part No.Max O/P Freq.DS1073M/Z-100 100.000MHz
DS1073M/Z-8080.000MHzDS1073M/Z-6666.667MHz
DS1073M/Z-6060.000MHz
DESCRIPTIONThe DS1073 is a fixed-frequency oscillator requiring no external components for operation. Numerous
operating frequencies are possible in the range of approximately 27.3kHz to 100MHz through the use of
an on-chip programmable prescaler and divider.
The DS1073 features a master oscillator followed by a prescaler and then a programmable divider. The
prescaler and programmable divider are user-programmable with the desired values being stored in non-
volatile memory. This allows the user to buy an off the shelf component and program it on site prior to
board production. Design changes can be accommodated on the fly by simply programming different
values into the device (or reprogramming previously programmed devices).
The DS1073 is shipped from the factory configured for half the maximum operating frequency. Contact
the factory for specially programmed devices. As alternatives to the onboard oscillator an external clock
signal or a crystal may be used as a reference. The choice of reference source (internal or external) is
user-selectable at the time of programming (or on the fly if the SEL mode is chosen).
The DS1073 features a dual-purpose I/O pin. If the device is powered up in Program mode this pin can be
used to input serial data to the on chip registers. After a Write command this data is stored in non-volatile
memory. When the chip is subsequently powered up in operating mode these values are automatically
restored to the on-chip registers and the I/O pin becomes the oscillator output.
DS1073
3V EconOscillator/DividerI/O
OUT0
VCC
GND
OSCIN
PDN/SELX
XTAL
DS1073Z-XXX150-mil SOIC
DS1073M-XXX300-mil DIP
XXX = Frequency option
DS1073
The DS1073 is available in 8-pin DIP or SOIC packages, allowing the generation of a clock signal easily,
economically and using minimal board area.
BLOCK DIAGRAM Figure 1
DS1073
PIN DESCRIPTIONS
IN/OUT Pin (I/O): This pin is the main oscillator output, with a frequency determined by clock
reference, M and N dividers. Except in programming mode this pin is always an output. In programming
mode this pin is an input and output.
External Oscillator Input (OSCIN): This pin can be used to supply an external reference frequency tothe device.
Crystal Oscillator Connection (XTAL): A crystal can be connected between this pin and OSCIN to
provide an alternative frequency reference. The crystal must be used in fundamental mode. If a crystal is
not used this pin should be left open.
Output Enable Function (OE pin): The DS1073 also features a “synchronous” output enable. When
OE is at a high logic level the oscillator free runs. When this pin is taken low OUT is held low,
immediately if OUT is already low, or at its next high-to-low transition if OUT is high. This prevents any
possible truncation of the output pulse width when the enable is used. While the output is disabled the
master oscillator continues to run (producing an output at OUT0, if the EN0 bit = 0) but the internalcounters (/N) are reset. This results in a constant phase relationship between OE’s return to a high level
and the resulting OUT signal. When the enable is released OUT will make its first transition within one
to two clock periods of the master clock.
Power-Down/Select Function (PDN/SELX
pin): The Power-Down/Select (PDN/SELX) pin has a user-
selectable function determined by one bit (PDN bit) of the user-programmable memory. According to
which function is selected, this pin will be referred to as PDN or SELX.
If the Power-Down function is selected (PDN bit = 1) a low logic level on this pin can be used to make
the device stop oscillating (active low) and go into a reduced power consumption state. The “Enabling
Sequencer” circuitry will first disable OUT in the same way as when OE is used. Next OUT0 will be
disabled in a similar fashion. Finally the oscillator circuitry will be disabled. In this mode both outputswill go into a high-impedance state.
The power consumption in the power-down state is much less than if OE is used because the internal
oscillator (if used) is completely powered down. Even if an external reference or a crystal is used all of
the on-chip buffers are powered down to minimize current drain. Consequently the device will takeconsiderably longer to recover (i.e., achieve stable oscillation) from a power-down condition than if the
OE is used.
If the Select function is chosen (PDN bit = 0) this pin can be used to switch between the internal
oscillator and an external reference (or crystal) on the fly. When this mode is chosen the E/I select bit is
overridden, a high logic level on SELX will select the internal oscillator, a low logic level will select the
external reference (or crystal oscillator).
Reference Output (OUT0 pin): A reference output, OUT0, is also available from the output of the
reference select mux. This output is especially useful as a buffered output of a crystal defined masterfrequency. OUT0 is unaffected by the OE pin, but is disabled in a glitchless fashion if the device is
powered down. If this output is not required it can be permanently disabled by setting the EN0 bit to 1,
and there will be a corresponding reduction in overall power consumption.
DS1073
USER-PROGRAMMABLE REGISTERSThe following registers can be programmed by the user to determine operating frequency and mode of
operation. Details of how these registers are programmed can be found in a later section, in this section
the function of the registers are described. The register settings are non-volatile, the values being stored
automatically in EEPROM when the registers are programmed. Note: The register bits cannot be used to
make mode or frequency changes on the fly. Changes can only be made by powering the device up in“Programming” mode. For them to be become effective the device must then be powered down and
powered up again in “Operation” mode.
For programming purposes the register bits are divided into two 9-bit words: the MUX word determines
mode of operation and prescaler values; the DIV word sets the value of the programmable divider.
MUX WORD Figure 2
(MSB) (LSB)*These bits must be set to 0
IThis bit selects either the internal oscillator or the external/ crystal reference.
1 = External/Crystal
0 = Internal Oscillator
however, if the PDN bit is set to 0 the E/I bit will be overridden by the logic level on the PDN/SELX pin.
Table 1
DIV1This bit allows the master clock to be routed directly to the output (DIV1 = 1). The N programmabledivider is bypassed so the programmed value of N is ignored. The frequency of the output (fOUT) will be
INTCLK or EXTCLK depending on which reference has been selected. If the Internal clock is selected
the M prescaler may still be used, so in this case fOUT = INTOSC/M (which also equals MCLK and
INTCLK). If DIV1 = 0 the programmable divider functions normally.
MSELThis bit determines whether or not the M prescaler is bypassed. MSEL = 1 will bypass the prescaler.
MSEL = 0 will switch in the prescaler, with a divide-by number determined by the M bit.
This bit sets the divide-by number for the prescaler. M = 0 results in divide-by-4, M = 1 results in divide-
DS1073
Table 2
*Assuming PDN bit = 1, otherwise internal/external selection will be controlled by the PDN/SELX pin.
DIV WORD Figure 3
(MSB) (LSB)
PDNThis bit is used to determine the function of the PDN/SELX pin. If PDN = 0, the PDN/SELX pin can be
used to determine the timing reference (either the internal oscillator or an external reference/crystal). If
PDN = 1, the PDN/SELX pin is used to put the device into power-down mode.
EN0This bit is used to determine whether the OUT0 pin is active or not. If EN0 = 1, OUT0 is disabled (High-
impedance). If EN0 = 0, the internal reference clock (MCLK) is output from OUT0. The OE pin has no
effect on OUT0, but OUT0 is disabled as part of the power-down sequence.
These nine bits determine the value of the programmable divider. The range of divisor values is from 2 to
513, and is equal to the programmed value of N plus 2:
Table 3
NOTE:The maximum value of N is constrained by the minimum output frequency. If the internal clock is
DS1073
OPERATION OF OUTPUT ENABLESince the output enable, internal master oscillator and/or external master oscillator are likely all
asynchronous there is the possibility of timing difficulties in the application. To minimize these
difficulties the DS1073 features an “enabling sequencer” to produce predictable results when the device is
enabled and disabled. In particular the output gating is configured so that truncated output pulses can
never be produced.
ENABLE TIMINGThe output enable function is produced by sampling the OE input with the output from the prescaler mux
(MCLK) and gating this with the output from the programmable divider. The exact behavior of the
device is therefore dependent on the setup time (tSU) from a transition on the OE input to the rising edgeof MCLK. If the actual setup time is less than tSUEM, then one more complete cycle of MCLK will be
required to complete the enable or disable operation (see diagrams). This is unlikely to be of any
consequence in most applications, and then only if the value for N is small. In general, the output will
make its first positive transition between approximately one and two clock periods of MCLK after the
rising edge of OE.
Figure 4
DISABLE TIMINGIf OE goes low while OUT is high, the output will be disabled on the completion of the output pulse. If
OUT is low, the disabling behavior will be dependent on the setup time between the falling edge of OE
and the rising edge of MCLK. If tSU < tSUEM the result will be one additional pulse appearing on the
output before disabling occurs.
If the device is in divide-by-one mode, the disabling occurs slightly differently. In this case if tSU > tSUEM
one additional output pulse will appear, if tSU < tSUEM then two additional output pulses will appear.
The following diagrams illustrate the timing in each of these cases.
Figure 5
DS1073
Figure 6
SELECT TIMINGIf the PDN bit is set to 0, the PDN/SELX pin can be used to switch between the internal oscillator and an
externalor crystal reference. The “Enabling Sequencer” is again employed to ensure this transition occurs
in a glitch-free fashion. Two asynchronous clock signals are involved, INTCLK is the internal reference
oscillator divided by one or whatever value of M is selected. EXTCLK is the clock signal fed into the
OSCIN pin, or the clock resulting from a crystal connected between OSCIN and XTAL. The behavior ofOUT0 is described in the following paragraphs, the OUT pin will behavior similarly but will be divided
by N.
FROM INTERNAL TO EXTERNAL CLOCKThis is accomplished by a high to low transition on the SELX pin. This transition is detected on the
falling edge of INTCLK. The output OUT0 will be held low for a minimum of half the period ofINTCLK (tI/2), then if EXTCLK is low it will be routed through to OUT0. If EXTCLK is high the
switching will not occur until EXTCLK returns to a low level.
Figure 7
Depending on the relative timing of the SELX signal and the internal clock, there may be up to one full
cycle of tI on the output after the falling edge of SELX. Then, the “low” time (tLOW) between output
pulses will be dependent on the relative timing between tI and tE. The time interval between the falling
edge of SELX and the first rising edge of the externally derived clock is tSIE. Approximate maximum and
minimum values of these parameters are:
tLOW (min) = tI/2
tLOW (max) = tI/2 + tEtSIE (min) = tI/2
tSIE (max) = 3tI/2 + tE
DS1073
FROM EXTERNAL TO INTERNAL CLOCKThis is accomplished by a low to high transition on the SELX pin. In this case the switch is leveltriggered, to allow for the possibility of a clock signal not being present at OSCIN. Note therefore, that if
a constant high-level signal is applied to OSCIN it will not be possible to switch over to the internal
reference. (Level triggering was not employed for the switch from internal to external reference as this
approach is slower and the internal clock may be running at a much higher frequency than the maximum
allowed external clock rate). When SELX is high and a low level is sensed on EXTCLK, OUT0 will be
held low until a falling edge occurs on INTCLK, then the next rising edge of INTCLK will be routedthrough to OUT0.
Figure 8
Depending on the relative timing of the SELX signal and the external clock, there may be up to one full
tEhigh period on the output after the rising edge of SELX. Then, the “low” time (tLOW) between output
pulses will be dependent on the relative timing between tI and tE. The time interval between the falling
edge of SELX and the first rising edge of the externally derived clock is tSIE. Approximate maximum and
minimum values of these parameters are:
tLOW (min) = tI/2
tLOW (max) = 3tI/2 + tElowtSIE (min) = tI/2
tSIE (max) = 3tI/2 + tEhigh
NOTE:In each case there will be a small additional delay due to internal propagation delays.
POWER-DOWN CONTROLIf the PDN bit is set to 1, the PDN/SELX pin can be used to power-down the device. If PDN is high the
device will run normally.
POWER-DOWNIf PDN is taken low a power-down sequence is initiated. The “Enabling Sequencer” is used to executeevents in the following sequence:
1. Disable OUT (same sequence as when OE is used) and reset N counters.
2. When OUT is low, switch OUT to high-impedance state.
3. Disable MCLK (and OUT0 if EN0 bit = 0), switch OUT0 to high impedance state.
4. Disable internal oscillator and OSCIN buffer.
DS1073
POWER-UPWhen PDN is taken to a high level the following power-up sequence occurs:
1. Enable internal oscillator and/or OSCIN buffer.
2. Set M and N to maximum values.
3. Wait approximately 256 cycles of MCLK for it to stabilize.
4. Reset M and N to programmed values.
5. Enable OUT0 (assuming EN0 bit = 0).
6. Enable OUT.
Steps 2 through 4 exist to allow the oscillator to stabilize before enabling the outputs.
Figure 9
POWER-ON RESETWhen power is initially applied to the device supply pin, a power-on reset sequence is executed, similarto that which occurs when the device is restored from a power-down condition. This sequence comprises
two stages, first a conventional POR to initialize all on-chip circuitry, followed by a stabilization period
to allow the oscillator to reach a stable frequency before enabling the outputs:
1. Initialize internal circuitry.
2. Enable internal oscillator and/or OSCIN buffer.
3. Set M and N to maximum values.
4. Wait approximately 256 cycles of MCLK for the oscillator to stabilize.
5. Load M and N programmed values from EEPROM.
6. Enable OUT0 (assuming EN0 = 0).
7. Enable OUT.
