DS1045S4 ,4 bit Dual Programmable Delay LineFEATURES PIN ASSIGNMENT All-silicon time delayIN 1 16 VCC Two programmable outputs from a singleV ..
DS1045S4 ,4 bit Dual Programmable Delay Lineapplications that do not require frequent reprogramming, the parallel inputs can be set using fixed ..
DS1045S-4 ,4 bit Dual Programmable Delay LineDS10454-Bit Dual Programmable Delay Linewww.dalsemi.com
DS1050 ,5 Bit Programmable, Pulse-Width Modulator: 1kHz, 5kHz, 10kHz, and 25kHzPIN DESCRIPTIONORDERING INFORMATIONDS1050Z-001 1kHz 8-Pin 150-mil SOIC V - 2.7V to 5.5V Power Suppl ..
DS1050 ,5 Bit Programmable, Pulse-Width Modulator: 1kHz, 5kHz, 10kHz, and 25kHzFEATURES PIN ASSIGNMENT Single 5-bit, programmable, pulse-widthmodulator (PWM)SCL V1 8 CC Adjusta ..
DS1050U-025 ,5-Bit, Programmable, Pulse-Width Modulator: 1kHz, 5kHz, 10kHz, and 25kHzDS10505-Bit, Programmable, Pulse-Width Modulator: 1kHz, 5kHz, 10kHz, and 25kHz
DT3316P-154MLD , SMT Power Inductors - DT3316P Series
DT3316P-154MLD , SMT Power Inductors - DT3316P Series
DT3316P-332MLD , SMT Power Inductors - DT3316P Series
DT3316P-334MLD , SMT Power Inductors - DT3316P Series
DT5A124E , Transistor Switch Digital Transistor Arrays (Inclusdes Resistors)
DT5A124E , Transistor Switch Digital Transistor Arrays (Inclusdes Resistors)
DS1045S-3+-DS1045S4-DS1045S-4
4-Bit, Dual, Programmable Delay Line
FEATURESAll-silicon time delayTwo programmable outputs from a single
input produce output-to-output delaysbetween 9 and 84 ns depending on device
typeProgrammable via four input pinsProgrammable increments of 3 to 5 ns with a
minimum of 9 ns and a maximum of 84 nsOutput pulse is a reproduction of input pulse
afterDelay with both leading and trailing edge
accuracyStandard 16-pin DIP or surface mount 16-pinSOICAuto-insertableLow-power CMOS design is TTL-compatible
PIN ASSIGNMENT
PIN DESCRIPTIONIN - Delay Line Input
OUTA, OUTB- Delay Line Outputs
A0-A3- Parallel Program Inputsfor OUT1
B0-B3- Parallel Program Inputs
for OUT2, EB- Enable A and B InputsVCC- +5V Input
GND - Ground
DESCRIPTIONThe DS1045 is a programmable silicon delay line having one input and two 4-bit programmable delay
outputs. Each 4-bit programmable output offers the user 16 possible delay values to select from, starting
with a minimum inherent DS1045 delay of 9 ns and a maximum achievable delay in the standard DS1045family of 84 ns. The standard DS1045 product line provides the user with three devices having uniform
delay increments of 3, 4, and 5 ns, depending on the device. Table 1 presents standard device family and
delay capability. Additionally, custom delay increments are available for special order through Dallas
Semiconductor.
The DS1045 is TTL and CMOS-compatible and capable of driving ten 74LS-type loads. The output
produced by the DS1045 is both rising and falling edge precise. The DS1045 programmable silicon
delay line has been designed as a reliable, economic alternative to hybrid programmable delay lines. It is
offered in a standard 16-pin auto-insertable DIP and a space-saving surface mount 16-pin SOIC package.
DS1045
4-Bit Dual Programmable Delay LineVCC
GND
VCC
OUTB
OUTAVCCVCCA2
GNDOUTB
OUTA
DS1045 16-Pin DIP
See Mech. Drawings
Section
DS1045S 16-Pin SOIC (300-mil)
See Mech. Drawings
Section
DS1045
PARALLEL PROGRAMMINGParallel programming of the DS1045 is accomplished via the set of parallel inputs A0-A3 and B0-B3 as
shown in Figure 1. Parallel input A0-A3 and B0-B3 accept TTL levels and are used to set the delay
values of outputs OUTA and OUTB, respectively. Sixteen possible delay values between the minimum
9 ns delay and the maxi-mum delay of the DS1045-x device version can be selected using the parallel
programming inputs A0-A3 or B0-B3 (see Table 2, “Delay vs. Programmed Input”). For example, theDS1045-3 outputs OUTA or OUTB and can be programmed to produce 16 possible delays between the
9 ns (minimum) and the 54 ns (maximum) in 3 ns increment levels.
For applications that do not require frequent reprogramming, the parallel inputs can be set using fixed
logic levels, as would be produced by jumpers, DIP switches, or TTL levels as produced by computersystems. Maximum flexibility in parallel programming can be achieved when inputs are set by computer-
generated data. By using the enable input pins for each respective programmed output and observing the
input setup (tDSE) and hold time (tDHE) requirements, data can be latched on an 8-bit bus. If the enable
pins, EA and EB, are not used to latch data, they should be set to a logic level 1. After each change inthe programmed delay value, a settling time (tEDV) or (tPDV) is required before the delayed output signal is
reliably produced. Since the DS1045 is a CMOS design, undefined input pins should be connected to
well defined logic levels and not left floating.
PART NUMBER TABLE Table 1
NOTE:Additional delay step times are available from Dallas Semiconductor by special order. Consult factory
for availability.
BLOCK DIAGRAM Figure 1
DS1045
DELAY VS. PROGRAMMED VALUE Table 2
DS1045 TEST CIRCUIT Figure 2
TEST SETUP DESCRIPTIONFigure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1045.The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected to the output. The DS1045 parallel
inputs are controlled by an interface to a central computer. All measurements are fully automated with
each instrument controlled by the computer over an IEEE 488 bus.
DS1045
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -1.0V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature -55°C to +125°C
Soldering Temperature See J-STD-020A specificationShort Circuit Output Current 50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(0°C to 70°C)
DC ELECTRICAL CHARACTERISTICS(0°C to 70°C; VCC 5V + 5%)
CAPACITANCE(TA = 25°C)
DS1045
TEST CONDITIONSTA=25°C ±=3°C
VCC= 5.0V ±=0.1V
Input Pulse = 3.0V high to 0.0V low ±=0.1V
Input Source Impedance = 50Ω maximum
Rise and fall times = 3.0 ns max. between 0.6V and 2.4V
Pulse Width = 250 ns
Period = 500 ns
Output Load = 74F04Measurement Point = 1.5V on inputs and outputs
Output Load Capacitance = 15 pF
NOTE:Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
TIMING DIAGRAM: NON-LATCHED PARALLEL MODE, EA
TIMING DIAGRAM: LATCHED PARALLEL MODE
DS1045
TIMING DIAGRAM: DS1045 INPUTS TO OUTPUTS
TERMINOLOGY
PERIOD: The time elapsed between the leading edge of the first pulse and the leading edge of thefollowing pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5Vpoint on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V on the leading edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of theinput pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of theinput pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the inputpulse and the 1.5V point on the leading edge of the output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of the output pulse.
NOTES:1. All voltages are referenced to ground.
2. @ VCC = 5V and 25°C. Delay accurate on both rising and falling edges within tolerances given in
Table 1.
