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DS1033
3-in-1 Low Voltage Silicon Delay Line
FEATURESAll-silicon timing circuitThree independent buffered delaysInitial delay tolerance ±1.5 nsStable and precise over temperature and
voltageLeading and trailing edge precision preserves
the input symmetryStandard 8-pin DIP, 8-pin SOICVapor phasing, IR and wave solderableAvailable in Tape and Reel
PIN ASSIGNMENT
PIN DESCRIPTIONIN1-IN3 - Input SignalsOUT1-OUT3 - Output Signals
NC - No Connection
VCC - Supply Voltage
GND - Ground
(Sub)- Internal substrateconnection, do not make
any external connections
to these pins
DESCRIPTIONThe DS1033 series is a low-power +3.3 Volt version of the DS1035. It is characterized for operation
over the range of 2.7V to 3.6V.
The DS1033 series of delay lines have three independent logic buffered delays in a single package. It is
available in a standard 8-pin DIP, 150-mil 8-pin mini-SOIC.
The device features precise leading and trailing edge accuracies. It has the inherent reliability of an all-
silicon delay line solution. The DS1033’s nominal tolerance is ±1.5 ns and an additional tolerance over
temperature and voltage of ±1.0 ns for the faster delays. Detailed specifications are shown in Table 1.
DS1033
3-in-1 Low Voltage Silicon Delay LineDS1033Z 8-Pin SOIC (150-mil)
See Mech. Drawings Section
GND
OUT3
DS1033
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (tPLH , tPHL) Table 1
NOTES:1. Nominal conditions are +25°C and VCC=+3.3 volts.
2. Temperature range of 0°C to 70°C.
3. Delay accuracy is for both leading and trailing edges.
DS1033
TEST SETUP DESCRIPTIONFigure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1033.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution ) connected to the output. The DS1033 output taps
are selected and connected to the interval counter by a VHF switch control unit. All measurements are
fully automated with each instrument controlled by the computer over an IEEE 488 bus.
DS1033 TEST CIRCUIT Figure 2
DS1033
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -1.0V to +6.0V
Operating Temperature 0°C to 70°C
Storage Temperature -55°C to +125°C
Soldering Temperature 260°C for 10 secondsShort Circuit Output Current 50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS(TA =0°C to 70°C)
AC ELECTRICAL CHARACTERISTICS(TA =+25°C)
CAPACITANCE(TA =+25°C)
DS1033
TEST CONDITIONSAmbient Temperature: 25°C ±=3°C
Supply Voltage (VCC):3.3V ±=0.1V
Input Pulse:
High: 3.0V ±=0.1V
Low: 0.0V ±=0.1V
Source Impedance: 50Ω=max.
Rise and Fall Time: 3.0 ns max. - Measured between 0.6V and 2.4V.Pulse Width: 500 ns
Pulse Period: 1 μs
Output Load Capacitance: 15 pF
Output: Each output is loaded with the equivalent of one 74F04 input gate.
Data is measured at the 1.5V level on the rising and falling edges.
Note: The above conditions are for test only and do not restrict the devices under other data sheet
conditions.
TIMING DIAGRAM
NOTES:1. All voltages are referenced to ground.
2. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application-sensitive with respect to de-coupling, layout, etc.
3. VCC=3.3V ±=10%.
4. VCC=2.7V.
DS1033
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of thefollowing pulse.
tWI(Pulse Width): The elapsed time on the pulse between the 1.5 volt point on the leading edge and the1.5 volt point on the trailing edge, or the 1.5 volt point on the trailing edge and the 1.5 volt point on theleading edge.
tRISE(Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of theinput pulse.
tFALL(Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge on theinput pulse.
tPLH(Time Delay, Rising): The elapsed time between the 1.5 volt point on the leading edge of the inputpulse and the 1.5 volt point on the leading edge of the output pulse.
tPHL(Time Delay, Falling): The elapsed time between the 1.5 volt point on the falling edge of the inputpulse and the 1.5 volt point on the falling edge of the output pulse.
