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DS1023-200-DS1023-200+-DS1023-500
8-Bit Programmable Timing Element
FEATURESStep sizes of 0.25 ns, 0.5 ns, 1 ns, 2 ns, 5 nsOn-chip reference delayConfigurable as delay line, pulse width
modulator, or free-running oscillatorCan delay clocks by a full period or moreGuaranteed monotonicityParallel or serial programmingSingle 5V supply16-pin DIP or SOIC package
PIN ASSIGNMENT
PIN DESCRIPTIONIN - Input
P0/Q - Parallel Input P0 (parallel mode)
- Serial Data Output (serial mode)
P1/CLK - Parallel Input P1 (parallel mode)- Serial Input Clock (serial mode)
P2/D - Parallel Input P2 (parallel mode)
- Serial Data Input (serial mode)
P3 - P7 - Remaining Parallel Inputs
GND - Ground
OUT/OUT - OutputREF/PWM - Reference or PWM Output/S - Parallel / Serial Programming
SelectMS - Output Mode Select
LE - Input Latch Enable
VCC - Supply Voltage
DESCRIPTIONThe DS1023 is an 8-bit programmable delay line similar in function to the DS1020/DS1021.
Additional features have been added to extend the range of applications:
The internal delay line architecture has been revised to allow clock signals to be delayed by up to a full
period or more. Combined with an on-chip reference delay (to offset the inherent or “step zero” delay of
DS1023
8-Bit Programmable Timing ElementQ/P0
CLK/P1
D/P2
GND
VCC
OUT/OUT
REF/PWM
P/S
DS1023 300-mil DIP
DS1023S 300-mil SOIC
DS1023
On-chip gating is provided to allow the device to provide a pulse width modulated output, triggered by
the input with duration set by the programmed value.
Alternatively the output signal may be inverted on chip, allowing the device to perform as a free-runningoscillator if the output is (externally) connected to the input.
PROGRAMMINGThe device programming is identical to the DS1020/DS1021. Note, however, that the serial clock and
data pins are shared with three of the parallel input pins.
The P/S pin controls the same function as “Mode Select” on the DS1020/DS1021 (but with reversed
polarity). A low logic level on this pin enables the parallel programming mode. LE must be at a high
logic level to alter the programmed value; when LE is taken low the data is latched internally and the
parallel data inputs may be altered without affecting the programmed value. This is useful for
multiplexed bus applications. For hard-wired applications LE should be tied to a high logic level.
When P/S is high serial programming is enabled. LE must be held high to enable loading or reading of
the internal register, during which time the delay is determined by the previously programmed value.Data is clocked in MSB to LSB order on the rising edge of the CLK input. Data transfer ends and the
new value is activated when LE is taken low.
PARALLEL MODE (P/S = 0)In the PARALLEL programming mode, the output of the DS1023 will reproduce the logic state of the
input after a delay determined by the state of the eight program input pins P0 - P7. The parallel inputs
can be programmed using DC levels or computer-generated data. For infrequent modification of thedelay value, jumpers may be used to connect the input pins to VCC or ground. For applications requiring
frequent timing adjustment, DIP switches may be used. The latch enable pin (LE) must be at a logic 1 in
hardwired implementations.
Maximum flexibility is obtained when the eight parallel programming bits are set using computer-generated data. When the data setup (tDSE) and data hold (tDHE) requirements are observed, the enable pin
can be used to latch data supplied on an 8-bit bus. Latch enable must be held at a logic 1 if it is not used
to latch the data. After each change in delay value, a settling time (tEDV or tPDV) is required before input
logic levels are accurately delayed.
SERIAL MODE (P/S = 1)In the SERIAL programming mode, the output of the DS1023 will reproduce the logic state of the input
after a delay time determined by an 8-bit value clocked into serial port D. While observing data setup
(tDSC) and data hold (tDHC) requirements, timing data is loaded in MSB-to-LSB order by the rising edge of
the serial clock (CLK). The latch enable pin (LE) must be at a logic 1 to load or read the internal 8-bit
input register, during which time the delay is determined by the last value activated. Data transfer endsand the new delay value is activated when latch enable (LE) returns to a logic 0. After each change, a
settling time (tEDV) is required before the delay is accurate.
As timing values are shifted into the serial data input (D), the previous contents of the 8-bit input register
are shifted out of the serial output pin (Q) in MSB-to-LSB order. By connecting the serial output of oneDS1023 to the serial input of a second DS1023, multiple devices can be daisy-chained (cascaded) for
DS1023
Applications can read the setting of the DS1023 Delay Line by connecting the serial output pin (Q) to the
serial input (D) through a resistor with a value of 1 to 10 kohms (Figure 2). Since the read process is
destructive, the resistor restores the value read and provides isolation when writing to the device. The
resistor must connect the serial output (Q) of the last device to the serial input (D) of the first device of adaisy chain (Figure 1). For serial readout with automatic restoration through a resistor, the device used to
write serial data must go to a high impedance state.
To initiate a serial read, latch enable (LE) is taken to a logic 1 while serial clock (CLK) is at a logic 0.
After a waiting time (tEQV), bit 7 (MSB) appears on the serial output (Q). On the first rising (0 --> 1)transition of the serial clock (CLK), bit 7 (MSB) is rewritten and bit 6 appears on the output after a time
tCQV. To restore the input register to its original state, this clocking process must be repeated eight times.
In the case of a daisy chain, the process must be repeated eight times per package. If the value read is
restored before latch enable (LE) is returned to logic 0, no settling time (tEDV) is required and the
programmed delay remains unchanged.
Since the DS1023 is a CMOS design, unused input pins (P3 - P7) must be connected to well-defined logic
levels; they must not be allowed to float. Serial output Q/P0 should be allowed to float if unused.
CASCADING MULTIPLE DEVICES (DAISY CHAIN) Figure 1
SERIAL READOUT Figure 2
REFERENCE DELAYIn all delay lines there is an inherent, or “step zero”, delay caused by the propagation delay through the
input and output buffers. In this device the step zero delay can be quite large compared to the delay step
size. To simplify system design a reference delay has been included on chip which may be used to
DS1023
For highest accuracy it is strongly recommended that the reference delay is used. Variations in input
voltage levels and transition times can significantly alter the measured delay from input to output. This
effect is totally removed if the reference delay output is used. Furthermore, adverse effects on step zero
delay caused by process temperature coefficients are also cancelled out.
INPUT PULSE DURATIONThe internal architecture of the DS1023 allows the output delay time to be considerably longer than theinput pulse width (see ac specifications). This feature is useful in many applications, in particular clock
phase control where delays up to and beyond one full clock period can be achieved.
MODE SELECTThe DS1023 has four possible output functions but only two output pins. The functionality of the two
output pins is determined by the Mode Select (MS) pin.
MS = 0 Figure 3
Output FunctionNamePin NumberReference OutputREF 9
Delayed OutputOUT15
OUT is a copy of the input waveform that is delayed by an amount set by the programmed values (Table1). A programmed value of zero will still result in a non-zero delay as indicated in the Step Zero delay
specification. The signal on OUT is the same polarity as the input.
REF is a fixed reference delay. It also is a copy of the input waveform but the delay interval is fixed to a
value approximately equal to the Step Zero Value of the device (as shown in the Reference Delayspecification). In fact the device is trimmed to ensure that the Reference Delay is always slightly longer
than the Step Zero Value (by 1.5 ns typically).
DS1023
MS = 1 Figure 4
Output FunctionNamePin NumberPulse Width Modulated OutputPWM 9
Delayed and Inverted OutputOUT15
PWM is an output triggered by the rising edge of the input waveform. After a time interval approximately
equal to the Step Zero delay of the device the PWM output will go high. The output will return to a lowlevel after a time interval determined by the programmed values (Table 1). Hence output pulse widths can
be obtained from (nearly) zero to the full delay range of the device. In practice the minimum output pulse
width is limited by the response time of the device to approximately 5ns. Programmed values less than
this will result in degradation of the output high level voltage until ultimately no discernible output pulse
is produced. The frequency/repetition rate of the output is determined by the input frequency. The inputpulse width can be shorter than the output pulse width, and is limited only by the minimum input pulse
width specification. The PWM function is not “re-triggerable”, subsequent input trigger pulses should
not be present until the output has returned to a low level.
OUT is an inverted copy of the input waveform that is delayed by an amount set by the programmed
values (Table 1). A programmed value of zero will still result in a non-zero delay as indicated in the Step
Zero delay specification. The OUT pin may also be externally connected to the input pin to produce afree-running oscillator. The frequency of oscillation is determined by the programmed delay value of the
device (see Table 2).
DS1023
FUNCTIONAL BLOCK DIAGRAM Figure 5
DELAY LINE DETAIL (CONCEPTUAL) - DS1023-200, DS1023-500 Figure 6
DS1023
DELAY LINE DETAIL (CONCEPTUAL) - DS1023-25, DS1023-50, DS1023-100Figure 7
PART NUMBER TABLE Table 11. In “Normal” mode (MS=0). Measured with respect to REF output. The minimum delay time is zero
(or less, by 1.5 ns typically)
2. In PWM mode (MS=1). The minimum output pulse width for reliable operation is 5 ns; programmed
values less than this may produce reduced output voltage levels or no output at all.
3. This is the deviation from a straight line drawn between the step zero value and the maximum
programmed delay time.
OSCILLATOR CONFIGURATION Table 24. Step size in output period (in ns).
5. Maximum output frequency depends on the actual step zero delay value, worst case values are shown
DS1023
DALLAS SEMICONDUCTOR TEST CIRCUIT Figure 8
TEST SETUP DESCRIPTIONFigure 8 illustrates the hardware configuration used for measuring the timing parameters of the DS1023.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected to the output. The DS1023 serial and
parallel ports are controlled by interfaces to a central computer. All measurements are fully automated
with each instrument controlled by the computer over an IEEE 488 bus.
TEST CONDITIONSINPUT:
Ambient Temperature:25°C ±=3°C
Supply Voltage (VCC):5.0V ±=0.1V
Input Pulse:High = 3.0V ±=0.1V
Low = 0.0V ±=0.1V
Source Impedance:50 ohms max.
Rise and Fall Time:3.0 ns max.(measured between
0.6V and 2.4V)
Pulse Width:500 ns
Period:1 μs
NOTE: Above conditions are for test only and do not restrict the operation of the device under other datasheet conditions.
OUTPUT:
Output is loaded with a 74F04. Delay is measured between the 1.5V level of the rising edge of the inputsignal and the 1.5V level of the corresponding edge of the output.
