DS1013S-75 ,3-in-1 Silicon Delay LineFEATURES PIN ASSIGNMENT All-silicon time delayIN 1 1 14 VCC 3 independent buffered delaysIN 1 1 1 ..
DS1013S-80 ,3-in-1 Silicon Delay LineDS10133-in-1 Silicon Delay Linewww.dalsemi.com
DS1013S-80+ ,3-in-1 Silicon Delay LineDS10133-in-1 Silicon Delay Linewww.dalsemi.com
DS1020-100 ,Programmable 8-Bit Silicon Delay LineApplications can read the setting of the DS1020 delay line by connecting the serial output pin (Q) ..
DS1020-100 ,Programmable 8-Bit Silicon Delay LinePIN DESCRIPTIONIN - Delay InputP0-P7 - Parallel Program PinsGND - GroundOUT - Delay OutputV - +5 Vo ..
DS1020-100 ,Programmable 8-Bit Silicon Delay Lineapplications requiringCCfrequent timing adjustment, DIP switches should be used. The enable pin (E) ..
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DT1608C-684MLD , Shielded Power Inductors - DT1608C
DT28F016SV-080 , 16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile MEMORY
DS1013M-100-DS1013M-15-DS1013M-150-DS1013M-150+-DS1013M-20-DS1013M-25-DS1013M-40-DS1013M-40+-DS1013M-60-DS1013S-10-DS1013S-100-DS1013S-100+-DS1013S-15-DS1013S-20-DS1013S-20/T&R-DS1013S-25-DS1013S-30-DS1013S-50-DS1013S-50+-DS1013S-60-DS1013S-60+-DS1013S-75-D
3-in-1 Silicon Delay Line
FEATURESAll-silicon time delay3 independent buffered delaysDelay tolerance ±2ns for -10 through –60Stable and precise over temperature and
voltage rangeLeading and trailing edge accuracyEconomicalAuto-insertable, low profileStandard 14-pin DIP, 8-pin DIP, or 16-pin
SOICLow-power CMOSTTL/CMOS-compatibleVapor phase, IR and wave solderableCustom delays availableQuick turn prototypesExtended temperature ranges available
PIN ASSIGNMENT
PIN DESCRIPTIONIN 1, IN 2, IN 3 - InputsOUT 1, OUT 2, OUT 3 - Outputs
GND- Ground
VCC- +5 Volts- No Connection
DESCRIPTIONThe DS1013 series of delay lines has three independent logic buffered delays in a single package. The
devices are offered in a standard 14-pin DIP which is pin-compatible with hybrid delay lines. Alternative
8-pin DIP and surface mount packages are available which save PC board area. Since the DS1013
products are an all silicon solution, better economy is achieved when compared to older methods using
hybrid techniques. The DS1013 series delay lines provide a nominal accuracy of ±2ns for delay timesranging from 10 ns to 60 ns, increasing to 5% for delays of 150 ns and longer. The DS1013 delay line
reproduces the input logic state at the output after a fixed delay as specified by the dash number extension
of the part number. The DS1013 is designed to reproduce both leading and trailing edges with equal
precision. Each output is capable of driving up to 10 74LS loads. Dallas Semiconductor can customize
standard products to meet special needs. For special requests and rapid delivery, call (972) 371–4348.
DS1013
3-in-1 Silicon Delay LineIN 1
IN 2
IN 3
GND
VCC
OUT 1
OUT 2
OUT 3
DS1013M 8-pin DIP (300-mil)
DS1013S 16-pin SOIC(300-mil)
IN 1
IN 2
IN 3
GND
OUT 3
OUT 2
OUT 1
VCC
IN 1
IN 2
IN 3
GND
OUT 3
OUT 2
OUT 1
VCC
DS1013 14-pin DIP (300-mil)
DS1013
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (tPHL, tPLH) Table 1Custom delays available
* ±3% tolerance** ±5% tolerance
DS1013
TIMING DIAGRAM: SILICON DELAY LINE Figure 2
TEST CIRCUIT Figure 3
DS1013
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground-1.0V to +7.0V
Operating Temperature0°C to 70°C
Storage Temperature-55°C to +125°C
Soldering Temperature260°C for 10 secondsShort Circuit Output Current50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS(0°C to 70°C; VCC = 5.0V ± 5%)
AC ELECTRICAL CHARACTERISTICS(TA = 25°C; VCC = 5V ± 5%)
CAPACITANCE(TA = 25°C)
DS1013
NOTES:1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VCC = 5V @ 25°C. Delays accurate on both rising and falling edges within ±2 ns for -10 to -60, ±3%for -70 to 100 and ±5% for -150 and longer delays.
4. See “Test Conditions” section.
5. The combination of temperature variations from 25°C to 0°C or 25°C to 70°C and voltage variationsfrom 5.0V to 4.75V or 5.0V to 5.25V may produce an additional delay shift of ±1.5 ns or ±3%,
whichever is greater.
6. All output delays tend to vary unidirectionally over temperature or voltage ranges (i.e., if OUT 1
slows down, all other outputs also slow down).
7. Period specifications may be exceeded; however, accuracy will be application-sensitive (decoupling,
layout, etc.).
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of thefollowing pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of theinput pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of theinput pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the inputpulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the inputpulse and the 1.5V point on the trailing edge of any tap output pulse.
DS1013
TEST SETUP DESCRIPTIONFigure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1013.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between each input and corresponding
output. Each output is selected and connected to the counter by a VHF switch control unit. All
measurements are fully automated, with each instrument controlled by a central computer over an IEEE488 bus.
TEST CONDITIONS
INPUT:Ambient Temperature:25°C ± 3°C
Supply Voltage (VCC):5.0V ± 0.1VInput Pulse:High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance:50 ohms Max.
Rise and Fall Time:3.0 ns Max.
Pulse Width:500 nsPeriod:1 µs
OUTPUT:Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:Above conditions are for test only and do not restrict the operation of the device under other data sheetconditions.
