DS1010-200 ,10-Tap Silicon Delay LinePIN DESCRIPTIONTAP 1 - TAP 10 - TAP Output NumberV - 5 VoltsCCGND - GroundNC - No ConnectionIN - In ..
DS1010-200 ,10-Tap Silicon Delay LineFEATURES PIN ASSIGNMENT All-silicon time delayIN1 1 14 VCC 10 taps equally spacedNC 2 13 TAP 1 D ..
DS1010-250 ,10-Tap Silicon Delay LineFEATURES PIN ASSIGNMENT All-silicon time delayIN1 1 14 VCC 10 taps equally spacedNC 2 13 TAP 1 D ..
DS1010-300 ,10-Tap Silicon Delay LinePIN DESCRIPTIONTAP 1 - TAP 10 - TAP Output NumberV - 5 VoltsCCGND - GroundNC - No ConnectionIN - In ..
DS1010-350 ,10-Tap Silicon Delay LineFEATURES PIN ASSIGNMENT All-silicon time delayIN1 1 14 VCC 10 taps equally spacedNC 2 13 TAP 1 D ..
DS1010-50 ,10-Tap Silicon Delay LinePIN DESCRIPTIONTAP 1 - TAP 10 - TAP Output NumberV - 5 VoltsCCGND - GroundNC - No ConnectionIN - In ..
DT12-6 , Thermoelectric Cooler
DT1608C-102MLC , Shielded Power Inductors - DT1608C
DT1608C-104 , SMT Power Inductors - DT1608 Series
DT1608C-104 , SMT Power Inductors - DT1608 Series
DT1608C-104 , SMT Power Inductors - DT1608 Series
DT1608C-105MLC , Shielded Power Inductors - DT1608C
DS1010-100-DS1010-150-DS1010-175-DS1010-200-DS1010-250-DS1010-300-DS1010-350-DS1010-50-DS1010-500-DS1010-60-DS1010-75
10-Tap Silicon Delay Line
FEATURESAll-silicon time delay10 taps equally spacedDelays are stable and preciseLeading and trailing edge accuracyDelay tolerance ±5% or ±2 ns, whichever is
greaterEconomicalAuto-insertable, low profileStandard 14-pin DIP or 16-pin SOICLow-power CMOSTTL/CMOS-compatibleVapor phase, IR and wave solderableCustom delays availableFast turn prototypes
PIN ASSIGNMENT
PIN DESCRIPTIONTAP 1 - TAP 10- TAP Output Number
VCC- 5 Volts
GND- Ground- No ConnectionIN- Input
DESCRIPTIONThe DS1010 series delay line has ten equally spaced taps providing delays from 5 ns to 500 ns. The
devices are offered in a standard 14-pin DIP which is pin-compatible with hybrid delay lines.
Alternatively, a 16-pin SOIC is available for surface mount technology which reduces PC board area.Since the DS1010 is an all-silicon solution, better economy is achieved when compared to older methods
using hybrid techniques. The DS1010 series delay lines provide a nominal accuracy of ±5% or ±2 ns,
whichever is greater. The DS1010 reproduces the input logic state at the TAP 10 output after a fixed
delay as specified by the dash number extension of the part number. The DS1010 is designed to produce
both leading and trailing edge with equal precision. Each tap is capable of driving up to 10 74LS typeloads. Dallas Semiconductor can customize standard products to meet special needs. For special requests
and rapid delivery, call (972) 371-4348.
DS1010
10-Tap Silicon Delay LineDS1010S 16-Pin SOIC
(300-mil)
IN1
TAP 2
TAP 4
TAP 8
TAP 6
TAP 1
TAP 7
TAP 10
TAP 9
TAP 5
VCC
GND
TAP 3
DS1010 14-Pin DIP (300-mil)
IN1
TAP 2
TAP 6
TAP 4
GND
TAP 5
TAP 9
TAP 10
TAP 7
TAP 3
VCC
TAP 8
TAP 1
DS1010
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (tPHL, tPLH) Table 1Custom delays available.
DS1010
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground-1.0V to +7.0V
Operating Temperature0°C to 70°C
Storage Temperature-55°C to +125°C
Soldering Temperature260°C for 10 secondsShort Circuit Output Current50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS(0°C to 70°C; VCC = 5.0V ± 5%)
AC ELECTRICAL CHARACTERISTICS(TA = 25°C; VCC = 5V ± 5%)
CAPACITANCE(TA = 25°C)
DS1010
NOTES:1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VCC = 5V @ 25°C. Input-to-tap delays accurate on both rising and falling edges within ±2 ns or ±5%
whichever is greater.
4. See “Test Conditions” section.
5. For DS1010 delay lines with a TAP 10 delay of 100 ns or greater, temperature variations from 25°C
to 0°C or 70°C may produce an additional input-to-tap delay shift of ±2ns or ±3%, whichever is
greater.
6. For DS1010 delay lines with a TAP 10 delay less than 100 ns, temperature variations from 25°C to
0°C or 70°C may produce an additional input-to-tap delay shift of ±1 ns or ±9%, whichever is greater.
7. All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP
1 slows down, all other taps will also slow down; TAP 3 can never be faster than TAP 2.
8. Pulse width and period specifications may be exceeded; however, accuracy will be application-
sensitive (decoupling, layout, etc.).
9. Certain high-frequency applications not recommended for -50 in 16-pin package. Consult factory.
TIMING DIAGRAM: SILICON DELAY LINE Figure 2DS1010
TEST CIRCUIT Figure 3
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leadingedge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of theinput pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of theinput pulse.
tPLH (Time Delay Rising): The elapsed time between the 1.5V point on the leading edge of the inputpulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the inputpulse and the 1.5V point on the trailing edge of any tap output pulse.
DS1010
TEST SETUP DESCRIPTIONFigure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1010.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each
tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS
INPUT:Ambient Temperature:25°C ± 3°C
Supply Voltage (VCC):5.0V ± 0.1V
Input Pulse:High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance:50 ohm max.Rise and Fall Time:3.0 ns max.
Pulse Width:500 ns (1 µs for -500)
Period:1 µs ( 2 µs for -500)
OUTPUT:Each output is loaded with the equivalent of one 74FO4 input gate. Delay is measured at the 1.5V level
on the rising and falling edge.
NOTE:Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
