DS1007-7 ,7-1 Silicon Delay LineFEATURES PIN ASSIGNMENT All-silicon time delayIN1 1 16 IN3 7 independent buffered delaysOUT1 2 15 ..
DS1007S-2 ,7-in-1 Silicon Delay LineFEATURES PIN ASSIGNMENT All-silicon time delayIN1 1 16 IN3 7 independent buffered delaysOUT1 2 15 ..
DS100BR111SQE/NOPB ,Ultra Low Pwr 10.3 Gbps 2-Ch Repeaters w/ Input Equalization and Output De-Emphasis 24-WQFN -40 to 85Featuresemphasis driver with up to -12 dB and can drive– Receive Equalization up to +36 dBoutput vo ..
DS100DF410SQE/NOPB ,10GbE Quad Channel Retimer with Adaptive EQ, CDR and DFE 48-WQFN -40 to 85Features 3 DescriptionThe DS100DF410 is four channel retimers with1• Each Channel Independently Loc ..
DS1010-100 ,10-Tap Silicon Delay LineELECTRICAL CHARACTERISTICS (0°C to 70°C; V = 5.0V ± 5%)CCPARAMETER SYM TEST MIN TYP MAX UNITS NOTES ..
DS1010-150 ,10-Tap Silicon Delay LineDS101010-Tap Silicon Delay Linewww.dalsemi.com
DT12-6 , Thermoelectric Cooler
DT1608C-102MLC , Shielded Power Inductors - DT1608C
DT1608C-104 , SMT Power Inductors - DT1608 Series
DT1608C-104 , SMT Power Inductors - DT1608 Series
DT1608C-104 , SMT Power Inductors - DT1608 Series
DT1608C-105MLC , Shielded Power Inductors - DT1608C
DS1007-1-DS1007-2-DS1007-3-DS1007-7
7-1 Silicon Delay Line
FEATURESAll-silicon time delay7 independent buffered delaysDelay tolerance ±2 nsFour delays can be custom set between 3 ns
and 10 nsThree delays can be custom set between 9 ns
and 40 nsDelays are stable and preciseEconomicalAuto-insertable, low profileSurface mount 16-pin SOICLow-power CMOSTTL/CMOS-compatibleVapor phase, IR and wave solderableCustom specifications availableQuick turn prototypes
PIN ASSIGNMENT
PIN DESCRIPTIONIN1 - IN7- Inputs
Out1 – Out7- Outputs
GND- Ground
VCC- +5 Volts
DESCRIPTIONThe DS1007 7-in-1 Silicon Delay Line provides seven independent delay times which are set by Dallas
Semiconductor to the customer’s specification. The delay times can be set from 3 ns to 40 ns with an
accuracy of ±2 ns at room temperature. The device is offered in both a 16-pin DIP and a 16-pin SOIC.
Since the DS1007 is an all-silicon solution, better economy and reliability are achieved when compared toolder methods using hybrid technology. The DS1007 reproduces the input logic state at the output after
the fixed delay. Dallas Semiconductor can customize standard products to meet special needs. For special
requests and rapid delivery, call (972) 371–4348.
DS1007
7-1 Silicon Delay LineDS1007S 16-Pin SOIC
(300-mil)
IN1
OUT1
IN2
OUT2
IN5
VCC
IN6
GND
OUT6
IN3
OUT5
IN4
IN1
OUT1
IN2
OUT2
IN5
VCC
IN6
OUT3
GND
IN7
OUT6
OUT7
OUT4
IN3
OUT5
IN4
DS1007 16-Pin DIP (300-mil)See Mech. Drawings Section
DS1007
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (tPLH) Table 1Custom delays available. Out 1 through Out 4 can be custom set from 3 to 10 ns (leading edge only
accuracy). Out 5 through Out 7 can be set from 9 to 40 ns (both leading and trailing edge accuracy).
DS1007
TIMING DIAGRAM: SILICON DELAY LINE Figure 2
TEST CIRCUIT Figure 3
DS1007
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground-1.0V to +7.0V
Operating Temperature0°C to 70°C
Storage Temperature-55°C to +125°C
Soldering Temperature260°C for 10 secondsShort Circuit Output Current50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS(0°C to 70°C; VCC = 5.0V ± 5%)
AC ELECTRICAL CHARACTERISTICS(TA = 25°C; VCC = 5V ± 5%)
CAPACITANCE(TA = 25°C)
DS1007
NOTES:1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VCC = 5V @25°C. Delays accurate on rising edges within ±2 ns.
4. See Test Conditions below.
5. All output delays in the same speed output tend to vary unidirectionally with temperature or voltagerange (i.e., if Out 2 slows down, all other outputs also slow down).
6. Period specifications may be exceeded; however, accuracy will be application-sensitive (decoupling,
layout, etc.).
7. tPU = 0 ms for Out 1 through Out 4.
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of theinput pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of theinput pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the inputpulse and the 1.5V point on the leading edge of the corresponding output pulse.
TEST SETUP DESCRIPTIONFigure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1007.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each output. Eachoutput is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
DS1007
TEST CONDITIONS
INPUT:Ambient Temperature:25°C ± 3°CSupply Voltage (VCC):5.0V ± 0.1V
Input Pulse:High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance:50 ohm max.
Rise and Fall Time:3.0 ns max.Pulse Width:500 ns
Period:1 µs
OUTPUT:Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising edge.
NOTE:Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
