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DS1004
5-Tap High Speed Silicon Delay Line
FEATURESAll-silicon timing circuitFive delayed clock phases per inputPrecise tap-to-tap nominal delay tolerances of
±0.75 and ±1 nsInput-to-tap 1 delay of 5 nsNominal Delay tolerances of ±1.5 nsLeading and trailing edge precision preserves
the input symmetryCMOS design with TTL compatibilityStandard 8-pin DIP and 150 mil 8-pin SOICVapor phase, IR and wave solderableAvailable in Tape and Reel
PIN ASSIGNMENT
PIN DESCRIPTIONTAP 1-5- TAP Output Number
VCC- +5V Supply
GND- Ground- Input
DESCRIPTIONThe DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4, or 5 ns tap-to-tap delays within a
standard part family. The device is Dallas Semiconductor’s fastest 5-tap delay line. It is available in a
standard 8-pin DIP and 150 mil 8-pin mini-SOIC. The device features precise leading and trailing edge
accuracies and has the inherent reliability of an all-silicon delay line solution.
The DS1004 is specified for tap-to-tap tolerances as shown in Table 1. Each device has a minimum
input-to-tap 1 delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4, or 5 ns.
See Table 1 for details. Input to Tap Tolerance over temperature and voltage is ±1.5 ns in addition to the
nominal delay tolerance. Nominal tap-to-tap tolerances range from ±0.75 ns to ±1.0 ns. Each output iscapable of driving up to 10 LS loads.
For customers needing non-standard delay values, the Late Package Program (LPP) is available.
Customers may contact Dallas Semiconductor at (972) 371–4348 for further details.
DS1004
5-Tap High Speed
Silicon Delay LineTAP 2
TAP 4
GND
VCC
TAP 1
TAP 3
TAP 5
DS1004M 8-Pin DIP (300-mil)
TAP 2
TAP 4
GND
VCC
TAP 1
TAP 3
TAP 5
DS1004Z 8-Pin SOIC (150-mil)
DS1004
PART NUMBER TOLERANCE TABLE Table 1
NOTES:1. Nominal conditions are +25°C and VCC = +5.0V
2. Temperature and voltage variations cover the range from VCC=5.0V ±=5% and temperature range from
0°C to +70°C.
3. Delay accuracy for both leading and trailing edges.
PART NUMBER DELAY TABLE Table 2
LOGIC DIAGRAM
DS1004
DS1004 TEST CIRCUIT Figure 1
TEST SETUP DESCRIPTIONFigure 1 illustrates the hardware configuration used for measuring the timing parameters of the DS1004.The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected to the output. The DS1004 output taps
are selected and connected to the interval counter by a VHF switch control unit. All measurements are
fully automated with each instrument controlled by the computer over an IEEE 488 bus.
DS1004
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground-1.0V to +7.0V
Operating Temperature0°C to 70°C
Storage Temperature-55°C to +125°C
Soldering TemperatureSee J-STD-020A SpecificationShort Circuit Output Current50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions abovethose indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS(0°C to 70°C; VCC = 5.0V ± 5%)
AC ELECTRICAL CHARACTERISTICS(TA = 25°C; VCC = 5V ± 5%)
CAPACITANCE(TA = 25°C)
DS1004
NOTES:1. All voltages are referenced to ground.
2. VCC=5V and 25°C. Delay accuracy on both the rising and falling edges within tolerances given inTable 1.
3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application
sensitive with respect to decoupling, layout, etc.
TEST CONDITIONS
INPUT:Ambient Temperature:25°C ±=3°C
Supply Voltage (VCC):5.0V ±=0.1V
Input Pulse:High = 3.0V ±=0.1V
Low = 0.0V ±=0.1V
Source Impedance:50 ohm max.
Rise and Fall Time:3.0 ns max. (measured between 0.6V and 2.4V)
Pulse Width:500 ns
Pulse Period:1 μs
Output Load
Capacitance:15 pF
OUTPUT:Each output is loaded with the equivalent of one 74F04 input gate. Data is measured at the 1.5V level on
the rising and falling edge.
NOTE:Above conditions are for test only and do not restrict the devices under other data sheet conditions.
TIMING DIAGRAM: DS1004 INPUT TO OUTPUTS
DS1004
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leadingedge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of theinput pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of theinput pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the inputpulse and the 1.5V point on the leading edge of the output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the falling edge of the input
pulse and the 1.5V point on the falling edge of the output pulse.
