DS1000-150 ,5-Tap Silicon Delay LinePIN DESCRIPTIONTAP 1-TAP 5 - TAP Output NumberV - +5 VoltsCCGND - GroundNC - No ConnectionIN - Inpu ..
DS1000-175 ,5-Tap Silicon Delay LineFEATURES PIN ASSIGNMENT All-silicon time delayIN 1 14 VCC 5 taps equally spaced1IN 8 VCCNC 2 13 N ..
DS1000-200 ,5-Tap Silicon Delay LineELECTRICAL CHARACTERISTICS (0°C to 70°C; V = 5.0V ± 5%)CCPARAMETER SYM TEST MIN TYP MAX UNITS NOTES ..
DS1000-25 ,5-Tap Silicon Delay LineELECTRICAL CHARACTERISTICS (0°C to 70°C; V = 5.0V ± 5%)CCPARAMETER SYM TEST MIN TYP MAX UNITS NOTES ..
DS1000-25 ,5-Tap Silicon Delay LineELECTRICAL CHARACTERISTICS (0°C to 70°C; V = 5.0V ± 5%)CCPARAMETER SYM TEST MIN TYP MAX UNITS NOTES ..
DS1000-250 ,5-Tap Silicon Delay LinePIN DESCRIPTIONTAP 1-TAP 5 - TAP Output NumberV - +5 VoltsCCGND - GroundNC - No ConnectionIN - Inpu ..
DSS306-55Y5S102M100 , FERRITE BEAD INDUCTORS, EMI SUPPRESSION FILTER COMPACT DISC-TYPE
DSS3540M-7B , 40V LOW VCE(sat) PNP SURFACE MOUNT TRANSISTOR
DSS4140V-7 , LOW VCE(SAT) NPN SURFACE MOUNT TRANSISTOR
DSS4160U-7 , LOW VCE(SAT) NPN SURFACE MOUNT TRANSISTOR
DSS4160V-7 , LOW VCE(SAT) NPN SURFACE MOUNT TRANSISTOR
DSS4240V-7 , LOW VCE(SAT) NPN SURFACE MOUNT TRANSISTOR
DS1000-100-DS1000-125-DS1000-150-DS1000-175-DS1000-200-DS1000-25-DS1000-250-DS1000-30-DS1000-35-DS1000-40-DS1000-50-DS1000-500-DS1000-60-DS1000-75
5-Tap Silicon Delay Line
FEATURESAll-silicon time delay5 taps equally spacedDelays are stable and preciseBoth leading and trailing edge accuracyDelay tolerance ±5% or ±2 ns, whichever is
greaterLow-power CMOSTTL/CMOS-compatibleVapor phase, IR and wave solderableCustom delays availableFast turn prototypesExtended temperature range available
(DS1000-IND)
PIN ASSIGNMENT
PIN DESCRIPTIONTAP 1-TAP 5- TAP Output Number
VCC- +5 Volts
GND- Ground- No ConnectionIN- Input
DESCRIPTIONThe DS1000 series delay lines have five equally spaced taps providing delays from 4 ns to 500 ns. These
devices are offered in a standard 14-pin DIP that is pin-compatible with hybrid delay lines. Alternatively,
8-pin DIPs and surface mount packages are available to save PC board area. Low cost and superiorreliability over hybrid technology is achieved by the combination of a 100% silicon delay line and
industry standard DIP and SOIC packaging. In order to maintain complete pin compatibility, DIP
packages are available with hybrid lead configurations. The DS1000 series delay lines provide a nominal
accuracy of ±5% or ±2 ns, whichever is greater. The DS1000 5-Tap Silicon Delay Line reproduces the
input logic state at the output after a fixed delay as specified by the extension of the part number after thedash. The DS1000 is designed to reproduce both leading and trailing edges with equal precision. Each
tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to
meet special needs. For special requests and rapid delivery, call 972-371-4348.
DS1000
5-Tap Silicon Delay LineTAP 2
TAP 4
GND
TAP 5
TAP 3
TAP 1
VCC
DS1000 14-Pin DIP (300-mil)See Mech. Drawings Section
TAP 2
TAP 4
GND
VCC
TAP 1
TAP 3
TAP 5
DS1000M 8-Pin DIP (300-mil)
TAP 2
TAP 4
GND
VCC
TAP 1
TAP 3
TAP 5
DS1000Z 8-Pin SOIC (150-mil)
DS1000
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (all values in ns) Table 1
DC ELECTRICAL CHARACTERISTICS(0°C to 70°C; VCC = 5.0V ± 5%)
AC ELECTRICAL CHARACTERISTICS(TA = 25°C; VCC = 5V ± 5%)
DS1000
CAPACITANCE(TA = 25°C)
NOTES:1. Initial tolerances are ±=with respect to the nominal value at 25°C and 5V.
2. Temperature tolerance is ±=with respect to the initial delay value over a range of 0°C to 70°C.
3. The delay will also vary with supply voltage, typically by less than 4% over the range 4.75 to 5.25V.
4. All tap delays tend to vary uni-directionally with temperature or voltage changes. For example, ifTAP 1 slows down, all other taps also slow down; TAP3 can never be faster than TAP2.
5. Intermediate delay values and packaging variations are available on a custom basis. For further
information, call 972-371–4348.
6. All voltages are referenced to ground.
7. Measured with outputs open.
8. Pulse width and period specifications may be exceeded; however, accuracy may be impaireddepending on application (decoupling, layout, etc.). The device will remain functional with pulse
widths down to 20% of Tap 5 delay, and input periods as short as 2(tWI).
9. ICC is a function of frequency and TAP 5 delay. Only a -25 operating with a 40-ns period and VCC =
5.25V will have an ICC = 75 mA. For example a -100 will never exceed 30 mA, etc.
10. See “Test Conditions” section at the end of this data sheet.
TIMING DIAGRAM: SILICON DELAY LINE Figure 2
DS1000
TEST CIRCUIT Figure 3
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of thefollowing pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of theinput pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of theinput pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the inputpulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the inputpulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTIONFigure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1000.
The input waveform is produced by a precision pulse generator under software control. Time delays aremeasured by a time interval counter (20 ps resolution) connected between the input and each tap. Each
tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
DS1000
TEST CONDITIONS
INPUT:Ambient Temperature:25°C ±=3°C
Supply Voltage (VCC):5.0V ±=0.1V
Input Pulse:High = 3.0V ±=0.1V
Low = 0.0V ±=0.1V
Source Impedance:50 ohm Max.
Rise and Fall Time:3.0 ns Max. (measured between 0.6V and 2.4V)
Pulse Width:500 ns (1 μs for -500)
Period:1 μs (2 μs for -500)
OUTPUT:Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
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