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DP8571AN
Timer Clock Peripheral (TCP)
TL/F/9979
DP8571A
Timer
Clock
Peripheral
(TCP)
May 1993
DP8571A Timer Clock Peripheral (TCP)
General Description
The DP8571Ais intendedforusein microprocessor based
systems whereinformationis requiredfor multi-tasking, data
loggingor general timeof day/date information. This device implementedinlow voltage silicon gate microCMOS tech-
nologyto providelow standby powerin battery back-upen-
vironments. The circuit’s architectureis such thatit looks
likea contiguous blockof memoryor I/Oports.The address
spaceis organizedas2 software selectable pagesof32
bytes. This includesthe Control Registers,the Clock Coun-
ters,the Alarm Compare RAM,the Timers and their data
RAM,andthe Time Save RAM.Anyofthe RAM locations
thatarenot being usedfor their intended purpose maybe
usedas general purpose CMOS RAM.
Timeand dateare maintained from 1/100ofa secondto
yearand leap yearina BCD format,12or24 hour modes.
Dayof week, dayof month anddayof year countersare
provided. Timeis controlledbyan on-chip crystal oscillator
requiring onlythe additionofthe crystalandtwo capacitors.
The choiceof crystal frequencyis program selectable.
Two independent multifunction10 MHz 16-bit timersare
provided. These timers operatein four modes. Eachhasits
own prescalerandcan selectanyof7 possible clock inputs.
Thus,by programmingthe input clocksandthe timer coun-
ter valuesa very wide rangeof timing durations canbe
achieved.The rangeis from about400ns (4.915 MHz oscil-
lator)to 65,535 seconds(18 hrs.,12 min.).
Power failurelogicand controlfunctionshavebeen integrat-on chip.This logicis usedbythe TCP toissuea powerfail
interrupt, andlockoutthemp interface.The time power fails
maybe loggedinto RAM automatically when VBBl VCC.
Additionally, two supply pins are provided. When VBB VCC, internal circuitrywill automatically switch fromthe
main supplytothe battery supply. Statusbitsare provided indicate initial applicationof battery power, system power,
andlow batterydetect. (Continued)
Features Full functionreal time clock/calendar 12/24 hour mode timekeepingDayof weekanddayof years counters Four selectable oscillator frequencies Parallel resonant oscillator Two 16-bit timers10 MHz external clock frequency Programmable multi-function output Flexible re-trigger facilities Powerfail features Internal power supply switchto external battery Power SupplyBus glitch protection Automaticlogof timeinto RAMat power failure On-chip interrupt structure Periodic, alarm, timerand powerfail interruptsUpto44 bytesof CMOS RAM INTR/MFO pins programmable High/Low and push-pull open drain
Block Diagram
TL/F/9979–1
FIGURE1
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
