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DP84910VHG-36
Integrated Read Channel
TL/F/11777
DP84910
(-36/-50)
Integrated
Read
Channel
October 1994
DP84910 (-36/-50)
Integrated Read Channel
General Description
The DP84910 integrates most functionsofthe hard disk
read channel electronics ontoa single5V chip.It incorpo-
ratesa pulse/servo detector,a programmable integrated
channel filter,a data synchronizer,a frequency synthesizer,
anda serial port interface. The chip receives data froma
read preamplifier, filtersand peak detectsthe read pulses
for both dataand embedded servo information and resyn-
chronizesthe data withthe system clock.
The DP84910is availableintwo versions, DP84910VHG-36
and DP84910VHG-50.The DP84910VHG-36is specifiedto
operate overa data rate rangeof 7.5 Mbits/secto Mbits/sec. The other version, DP84910VHG-50,willop-
erate overa datarate rangeof 13.7 Mbits/secto50 Mbits/
sec.
This deviceis specifically designedto address zoned data
rate applications.A channel filter with control registerse-
lectable cutoff frequency and equalizationis providedon-
chip. This eliminatesthe needfor multiple external channel
filters and allowsfor greater flexibilityinthe selectionof
zone frequencies.The frequency synthesizer provides cen-
ter frequency informationforthe data synchronizer anda
variable frequency write clock. Thereisno needforanyoff-
chip frequency setting componentsor DACs. four-bank control registeris includedto control zoning
operations and configure general chip functions.At VCC
power-upthe chipself-configuresby presettingallbits inthe
control registerto predetermined operating setup condi-
tions.
Independent power down controlforallofthe major blocks
withinthe chipis providedvia three bitsinthe control
register (SYNCÐPWRÐDN, STHÐPWRÐDN and
PDÐPWRÐDN)to manage power consumption.In addi-
tion,two pins (SLEEPand IDLE/SERVO)are availableto
control power management. The sleep modepin (SLEEP)
powers downall circuitryonthe chip includingthe control
register.Inthis modethe maximum power supply currentis mA;the control register data mustbe reentered when
exitingthis mode.The idle/servo modepin (IDLE/SERVO)
togglesthe device betweenthe idleand servo modes.Inthe
idle mode, onlythe control registerand pulse detector bias-
ing circuitry necessaryfora quick recoveryare active.Inthe
servo mode,the pulse detector portions neededfor servo
detectionare activeas wellasthe control register. Less
than15msis requiredforthe pulse detectorto recover from
theidle condition. The control register dataisnotlost when
thispinis toggled.Thepincanbe rapidly toggled (k15ms) achieve average power consumption savings andwill
keepthe read/write headon track. Seventeen power and
ground pinsare providedto isolate major functional blocks
and allowfor independent supply voltage filtering, thusen-
hancing noise immunity. (Continued)
TL/F/11777–1
FIGURE1. DP84910ina Typical Disk DriveSystem
MICROWIRETMis atrademarkof National SemiconductorCorporation.
C1996National SemiconductorCorporation RRD-B30M116/Printed inU.S.A. http://
